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基于TI公司的AM3359并行冗余协议(PRP)以太网参考设计

来源：中电网

2018-10-15

类别：工业控制

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拍明

原标题：TI AM3359并行冗余协议(PRP)以太网参考设计

　　TI公司的AM3359是基于ARM Cortex-A8处理器的微处理器,具有增强的图像图形处理以及外设和工业接口选择如EtherCAT和PROFIBUS,器件支持高级操作系统(HLOS).工作频率高达1GHz,NEON™ SIMD协处理器,集成了32KB L1指令和32KB数据缓存,带误差修正码(ECC)的256KB L2缓存,176KB引导ROM,64KB专用RAM以及中断控制器.主要用在游戏外设,家庭和工业自动化,消费类医疗电器,打印机,智能玩具系统,连接的售货机和称重仪.本文介绍了AM3359主要特性和功能框图,以及用于变电站自动化的并行冗余协议(PRP)以太网参考设计TIDEP0054主要特性,框图,电路图,材料清单和PCB设计图.

　　The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image,graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. Thedevices support high-level operating systems (HLOS). Linux® and Android™ are available free of chargefrom TI.

　　The AM335x microprocessor contain the subsystems sand a brief description of each follows:

　　The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVRSGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gamingeffects.

　　The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greaterefficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocolssuch as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others.

　　Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and allsystem-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specializeddata handling operations, custom peripheral interfaces, and in offloading tasks from the other processorcores of SoC.

　　AM3359主要特性:

　　• Up to 1-GHz Sitara™ ARM® Cortex®-A8 32‑BitRISC Processor

　　– NEON™ SIMD Coprocessor

　　– 32KB of L1 Instruction and 32KB of Data CacheWith Single-Error Detection (Parity)

　　– 256KB of L2 Cache With Error Correcting Code(ECC)

　　– 176KB of On-Chip Boot ROM

　　– 64KB of Dedicated RAM

　　– Emulation and Debug - JTAG

　　– Interrupt Controller (up to 128 InterruptRequests)

　　• On-Chip Memory (Shared L3 RAM)

　　– 64KB of General-Purpose On-Chip MemoryController (OCMC) RAM

　　– Accessible to All Masters

　　– Supports Retention for Fast Wakeup

　　• External Memory Interfaces (EMIF)

　　– mDDR(LPDDR), DDR2, DDR3, DDR3LController:

　　• mDDR: 200-MHz Clock (400-MHz DataRate)

　　• DDR2: 266-MHz Clock (532-MHz Data Rate)

　　• DDR3: 400-MHz Clock (800-MHz Data Rate)

　　• DDR3L: 400-MHz Clock (800-MHz DataRate)

　　• 16-Bit Data Bus

　　• 1GB of Total Addressable Space

　　• Supports One x16 or Two x8 Memory DeviceConfigurations

　　– General-Purpose Memory Controller (GPMC)

　　• Flexible 8-Bit and 16-Bit AsynchronousMemory Interface With up to Seven ChipSelects (NAND, NOR, Muxed-NOR, SRAM)

　　• Uses BCH Code to Support 4-, 8-, or 16-BitECC

　　• Uses Hamming Code to Support 1-Bit ECC

　　– Error Locator Module (ELM)

　　• Used in Conjunction With the GPMC toLocate Addresses of Data Errors fromSyndrome Polynomials Generated Using aBCH Algorithm

　　• Supports 4-, 8-, and 16-Bit per 512-ByteBlock Error Location Based on BCHAlgorithms

　　• Programmable Real-Time Unit Subsystem andIndustrial Communication Subsystem (PRU-ICSS)

　　– Supports Protocols such as EtherCAT®,PROFIBUS, PROFINET, EtherNet/IP™, and

　　– Two Programmable Real-Time Units (PRUs)

　　• 32-Bit Load/Store RISC Processor Capableof Running at 200 MHz

　　• 8KB of Instruction RAM With Single-ErrorDetection (Parity)

　　• 8KB of Data RAM With Single-ErrorDetection (Parity)

　　• Single-Cycle 32-Bit Multiplier With 64-BitAccumulator

　　• Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch onExternal Signal

　　– 12KB of Shared RAM With Single-ErrorDetection (Parity)

　　– Three 120-Byte Register Banks Accessible byEach PRU

　　– Interrupt Controller (INTC) for Handling SystemInput Events

　　– Local Interconnect Bus for Connecting Internaland External Masters to the Resources Insidethe PRU-ICSS

　　– Peripherals Inside the PRU-ICSS:

　　• One UART Port With Flow Control Pins,Supports up to 12 Mbps

　　• One Enhanced Capture (eCAP) Module

　　• Two MII Ethernet Ports that SupportIndustrial Ethernet, such as EtherCAT

　　• One MDIO Port

　　• Power, Reset, and Clock Management (PRCM)Module

　　– Controls the Entry and Exit of Stand-By andDeep-Sleep Modes

　　– Responsible for Sleep Sequencing, PowerDomain Switch-Off Sequencing, Wake-Up

　　Sequencing, and Power Domain Switch-OnSequencing

　　– Clocks

　　• Integrated 15- to 35-MHz High-FrequencyOscillator Used to Generate a Reference

　　Clock for Various System and PeripheralClocks

　　• Supports Individual Clock Enable andDisable Control for Subsystems andPeripherals to Facilitate Reduced PowerConsumption

　　• Five ADPLLs to Generate System Clocks(MPU Subsystem, DDR Interface, USB and

　　Peripherals [MMC and SD, UART, SPI, I2C],L3, L4, Ethernet, GFX [SGX530], LCD Pixel

　　Clock)

　　– Power

　　• Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic[WAKEUP])

　　• Three Switchable Power Domains (MPUSubsystem [MPU], SGX530 [GFX],Peripherals and Infrastructure [PER])

　　• Implements SmartReflex™ Class 2B forCore Voltage Scaling Based On DieTemperature, Process Variation, andPerformance (Adaptive Voltage Scaling[AVS])

　　• Dynamic Voltage Frequency Scaling (DVFS)

　　• Real-Time Clock (RTC)

　　– Real-Time Date (Day-Month-Year-Day of Week)and Time (Hours-Minutes-Seconds) Information

　　– Internal 32.768-kHz Oscillator, RTC Logic and1.1-V Internal LDO

　　– Independent Power-on-Reset(RTC_PWRONRSTn) Input

　　– Dedicated Input Pin (EXT_WAKEUP) forExternal Wake Events

　　– Programmable Alarm Can be Used to GenerateInternal Interrupts to the PRCM (for Wakeup) orCortex-A8 (for Event Notification)

　　– Programmable Alarm Can be Used WithExternal Output (PMIC_POWER_EN) to Enablethe Power Management IC to Restore Non-RTCPower Domains

　　• Peripherals

　　– Up to Two USB 2.0 High-Speed OTG PortsWith Integrated PHY

　　– Up to Two Industrial Gigabit Ethernet MACs (10,100, 1000 Mbps)

　　• Integrated Switch

　　• Each MAC Supports MII, RMII, RGMII, andMDIO Interfaces

　　• Ethernet MACs and Switch Can OperateIndependent of Other Functions

　　• IEEE 1588v2 Precision Time Protocol (PTP)

　　– Up to Two Controller-Area Network (CAN) Ports

　　• Supports CAN Version 2 Parts A and B

　　– Up to Two Multichannel Audio Serial Ports(McASPs)

　　• Transmit and Receive Clocks up to 50 MHz

　　• Up to Four Serial Data Pins per McASP PortWith Independent TX and RX Clocks

　　• Supports Time Division Multiplexing (TDM),Inter-IC Sound (I2S), and Similar Formats

　　• Supports Digital Audio Interface

　　Transmission (SPDIF, IEC60958-1, andAES-3 Formats)

　　• FIFO Buffers for Transmit and Receive (256Bytes)

　　– Up to Six UARTs

　　• All UARTs Support IrDA and CIR Modes

　　• All UARTs Support RTS and CTS FlowControl

　　• UART1 Supports Full Modem Control

　　– Up to Two Master and Slave McSPI SerialInterfaces

　　• Up to Two Chip Selects

　　• Up to 48 MHz

　　– Up to Three MMC, SD, SDIO Ports

　　• 1-, 4- and 8-Bit MMC, SD, SDIO Modes

　　• MMCSD0 has Dedicated Power Rail for1.8‑V or 3.3-V Operation

　　• Up to 48-MHz Data Transfer Rate

　　• Supports Card Detect and Write Protect

　　• Complies With MMC4.3, SD, SDIO 2.0Specifications

　　– Up to Three I2C Master and Slave Interfaces

　　• Standard Mode (up to 100 kHz)

　　• Fast Mode (up to 400 kHz)

　　– Up to Four Banks of General-Purpose I/O(GPIO) Pins

　　• 32 GPIO Pins per Bank (Multiplexed WithOther Functional Pins)

　　• GPIO Pins Can be Used as Interrupt Inputs(up to Two Interrupt Inputs per Bank)

　　– Up to Three External DMA Event Inputs that canAlso be Used as Interrupt Inputs

　　– Eight 32-Bit General-Purpose Timers

　　• DMTIMER1 is a 1-ms Timer Used forOperating System (OS) Ticks

　　• DMTIMER4–DMTIMER7 are Pinned Out

　　– One Watchdog Timer

　　– SGX530 3D Graphics Engine

　　• Tile-Based Architecture Delivering up to 20Million Polygons per Second

　　• Universal Scalable Shader Engine (USSE) isa Multithreaded Engine Incorporating Pixel

　　and Vertex Shader Functionality

　　• Advanced Shader Feature Set in Excess ofMicrosoft VS3.0, PS3.0, and OGL2.0

　　• Industry Standard API Support of Direct3DMobile, OGL-ES 1.1 and 2.0, OpenVG 1.0,and OpenMax

　　• Fine-Grained Task Switching, LoadBalancing, and Power Management

　　• Advanced Geometry DMA-Driven Operationfor Minimum CPU Interaction

　　• Programmable High-Quality Image Anti-Aliasing

　　• Fully Virtualized Memory Addressing for OSOperation in a Unified Memory Architecture

　　– LCD Controller

　　• Up to 24-Bit Data Output; 8 Bits per Pixel(RGB)

　　• Resolution up to 2048 × 2048 (WithMaximum 126-MHz Pixel Clock)

　　• Integrated LCD Interface Display Driver(LIDD) Controller

　　• Integrated Raster Controller

　　• Integrated DMA Engine to Pull Data from theExternal Frame Buffer Without Burdening the

　　Processor via Interrupts or a Firmware Timer

　　• 512-Word Deep Internal FIFO

　　• Supported Display Types:

　　– Character Displays - Uses LIDDController to Program these Displays

　　– Passive Matrix LCD Displays - Uses LCDRaster Display Controller to ProvideTiming and Data for Constant GraphicsRefresh to a Passive Display

　　– Active Matrix LCD Displays – UsesExternal Frame Buffer Space and theInternal DMA Engine to Drive StreamingData to the Panel

　　– 12-Bit Successive Approximation Register(SAR) ADC

　　• 200K Samples per Second

　　• Input can be Selected from any of the EightAnalog Inputs Multiplexed Through an 8:1

　　Analog Switch

　　• Can be Configured to Operate as a 4-Wire,5-Wire, or 8-Wire Resistive Touch Screen

　　Controller (TSC) Interface

　　– Up to Three 32-Bit eCAP Modules

　　• Configurable as Three Capture Inputs orThree Auxiliary PWM Outputs

　　– Up to Three Enhanced High-Resolution PWMModules (eHRPWMs)

　　• Dedicated 16-Bit Time-Base Counter WithTime and Frequency Controls

　　• Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge

　　Asymmetric Outputs

　　– Up to Three 32-Bit Enhanced QuadratureEncoder Pulse (eQEP) Modules

　　• Device Identification

　　– Contains Electrical Fuse Farm (FuseFarm) ofWhich Some Bits are Factory Programmable

　　• Production ID

　　• Device Part Number (Unique JTAG ID)

　　• Device Revision (Readable by Host ARM)

　　• Debug Interface Support

　　– JTAG and cJTAG for ARM (Cortex-A8 andPRCM), PRU-ICSS Debug

　　– Supports Device Boundary Scan

　　– Supports IEEE 1500

　　• DMA

　　– On-Chip Enhanced DMA Controller (EDMA) hasThree Third-Party Transfer Controllers (TPTCs)and One Third-Party Channel Controller(TPCC), Which Supports up to 64Programmable Logical Channels and EightQDMA Channels. EDMA is Used for:

　　• Transfers to and from On-Chip Memories

　　• Transfers to and from External Storage(EMIF, GPMC, Slave Peripherals)

　　• Inter-Processor Communication (IPC)

　　– Integrates Hardware-Based Mailbox for IPC andSpinlock for Process Synchronization BetweenCortex-A8, PRCM, and PRU-ICSS

　　• Mailbox Registers that Generate Interrupts

　　– Four Initiators (Cortex-A8, PRCM, PRU0,PRU1)

　　• Spinlock has 128 Software-Assigned LockRegisters

　　• Security

　　– Crypto Hardware Accelerators (AES, SHA,RNG)

　　– Secure Boot

　　• Boot Modes

　　– Boot Mode is Selected Through BootConfiguration Pins Latched on the Rising Edgeof the PWRONRSTn Reset Input Pin

　　• Packages:

　　– 298-Pin S-PBGA-N298 Via Channel Package(ZCE Suffix), 0.65-mm Ball Pitch

　　– 324-Pin S-PBGA-N324 Package(ZCZ Suffix), 0.80-mm Ball Pitch

　　AM3359应用:

　　• Gaming Peripherals

　　• Home and Industrial Automation

　　• Consumer Medical Appliances

　　• Printers

　　• Smart Toll Systems

　　• Connected Vending Machines

　　• Weighing Scales

　　• Educational Consoles

　　• Advanced Toys

　　图1. AM3359框图

　　用于变电站自动化的并行冗余协议(PRP)以太网参考设计

　　This TI Design is a solution for high reliability,low-latency network communications for substation-automation equipment in smart gridtransmission and distribution networks. It supports theParallel Redundancy Protocol (PRP) specification inthe IEC 62439 standard. This solution is a lower-costalternative to FPGA approaches and provides theflexibility and performance to add features such asIEC 61850 support without additional components.

　　A substation is a key component of the electricity-grid infrastructure, located everywhere from powergeneration facilities throughout the distribution network to the low-voltage feeders serving residences andbusinesses. Substations are a primary factor in transforming voltage levels for transmission andperforming important functions such as switching, monitoring, and protecting sub-systems in order tomaintain grid efficiency and reliability. Traditional-substation systems focused on fault monitoring that canbe manually fixed by switching to backup subsystems.

　　Consumers, regulators, and grid operators demand increasing reliability of electricity delivery. Theintroduction of automatic switching and protection of subsystems increases the demand for the automationof substation operations and communications to monitor grid conditions and communicate information togrid operators.

　　Operators need to continually monitor the health of networks and take action to maintain the operationwith efficiency. This need leads to the requirement for reliable and low-latency communications betweenthe control center of the operator and high-value nodes such as substations.

　　The International Electro-Technical Commission (IEC) released specifications for industrial-Ethernetcommunications under the IEC 62439 standard. The PRP specification is one of the IEC 62439-3standards that provides a static redundancy Ethernet-based protocol that supports critical real-timesystems that require continuous monitoring.

　　并行冗余协议(PRP)以太网参考设计主要特性:

　　• Compliant to IEC 62439-3 Clause 4 Specificationfor PRP-Ethernet Communications

　　• Traffic Filtering Based on Virtual Local-AreaNetwork (VLAN) IDs, Multicast and Broadcast

　　Support, and Built-in Storm Prevention andSupervision Mechanism

　　• Zero Recovery Time in Case of Network Failure

　　• Dual-Ported Full-Duplex 100-Mbps Ethernet

　　• Fully Programmable Solution Provides Platform forIntegration of Additional Applications

　　并行冗余协议(PRP)以太网参考设计特性应用:

　　• Substation and Distribution Automation

　　• Protection Relays

　　• Smart-Grid Communication

　　• Factory Automation

　　图2.并行冗余协议(PRP)以太网参考设计外形图

　　图3.并行冗余协议(PRP)以太网参考设计框图

　　图4.并行冗余协议(PRP)以太网参考设计系统架构图

　　并行冗余协议(PRP)以太网参考设计材料清单:

　　图19.并行冗余协议(PRP)以太网参考设计PCB设计图(1)

　　图20.并行冗余协议(PRP)以太网参考设计PCB设计图(2)

　　图21.并行冗余协议(PRP)以太网参考设计PCB设计图(3)

　　图22.并行冗余协议(PRP)以太网参考设计PCB设计图(4)

　　图23.并行冗余协议(PRP)以太网参考设计PCB设计图(5)

　　图24.并行冗余协议(PRP)以太网参考设计PCB设计图(6)

　　完成设计的核心器件

完成设计的核心器件.png

　　TPS3808

　　描述

　　The TPS3808 family of microprocessor supervisory circuits monitors system voltages from 0.4 V to 5 V, asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user-adjustable delay time after the SENSE voltage and manual reset (MR) return above the respective thresholds.

　　The TPS3808 device uses a precision reference to achieve 0.5% threshold accuracy for VIT ≤ 3.3 V. The reset delay time can be set to 20 ms by disconnecting the CT pin, 300 ms by connecting the CT pin to VDD using a resistor, or can be user-adjusted between 1.25 ms and 10 s by connecting the CT pin to an external capacitor. The TPS3808 device has a very low typical quiescent current of 2.4 µA, so it is well-suited to battery-powered applications. It is available in the SOT-23 and 2-mm × 2-mm WSON packages, and is fully specified over a temperature range of –40°C to 125°C (TJ).

　　特性

　　Power-On Reset Generator with Adjustable Delay

　　Time: 1.25 ms to 10 s

　　Very Low Quiescent Current: 2.4 µA Typical

　　High Threshold Accuracy: 0.5% Typ

　　Fixed Threshold Voltages for Standard Voltage

　　Rails from 0.9 V to 5 V and Adjustable Voltage

　　Down to 0.4 V Are Available

　　Manual Reset (MR) Input

　　Open-Drain RESET Output

　　Temperature Range: –40°C to 125°C

　　Small SOT-23 and 2-mm × 2-mm WSON

　　Packages

　　SN74LVC1G08

　　描述

　　This single 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.

　　The SN74LVC1G08 device performs the Boolean function or in positive logic.

　　The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

　　The SN74LVC1G08 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

　　特性

　　Available in the Ultra Small 0.64-mm2

　　Package (DPW) With 0.5-mm Pitch

　　Supports 5-V VCC Operation

　　Inputs Accept Voltages to 5.5 V

　　Provides Down Translation to VCC

　　Max tpd of 3.6 ns at 3.3 V

　　Low Power Consumption, 10-μA Max ICC

　　±24-mA Output Drive at 3.3 V

　　Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection

　　Latch-Up Performance Exceeds 100 mA

　　Per JESD 78, Class II

　　ESD Protection Exceeds JESD 22

　　2000-V Human-Body Model (A114-A)

　　200-V Machine Model (A115-A)

　　1000-V Charged-Device Model (C101)

　　MSP430F5528

　　描述

　　The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring peripheral sets targeted for a variety of applications. The architecture, combined with extensive low-power modes, is optimized to achieve extended battery life in portable measurement applications. The microcontroller features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the devices to wake up from low-power modes to active mode in 3.5 µs (typical).

　　The MSP430F5529, MSP430F5527, MSP430F5525, and MSP430F5521 microcontrollers have integrated USB and PHY supporting USB 2.0, four 16-bit timers, a high-performance 12-bit analog-to-digital converter (ADC), two USCIs, a hardware multiplier, DMA, an RTC module with alarm capabilities, and 63 I/O pins. The MSP430F5528, MSP430F5526, MSP430F5524, and MSP430F5522 microcontrollers include all of these peripherals but have 47 I/O pins.

　　The MSP430F5519, MSP430F5517, and MSP430F5515 microcontrollers have integrated USB and PHY supporting USB 2.0, four 16-bit timers, two USCIs, a hardware multiplier, DMA, an RTC module with alarm capabilities, and 63 I/O pins. The MSP430F5514 and MSP430FF5513 microcontrollers include all of these peripherals but have 47 I/O pins.

　　Typical applications include analog and digital sensor systems, data loggers, and others that require connectivity to various USB hosts.

　　For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User’s Guide

　　特性

　　Low Supply Voltage Range:

　　3.6 V Down to 1.8 V

　　Ultra-Low Power Consumption

　　Active Mode (AM):

　　All System Clocks Active:

　　290 µA/MHz at 8 MHz, 3.0 V, Flash Program Execution (Typical)

　　150 µA/MHz at 8 MHz, 3.0 V, RAM Program Execution (Typical)

　　Standby Mode (LPM3):

　　Real-Time Clock (RTC) With Crystal, Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wakeup:

　　1.9 µA at 2.2 V, 2.1 µA at 3.0 V (Typical)

　　Low-Power Oscillator (VLO), General-Purpose Counter, Watchdog, and Supply Supervisor Operational, Full RAM Retention, Fast Wakeup:

　　1.4 µA at 3.0 V (Typical)

　　Off Mode (LPM4):

　　Full RAM Retention, Supply Supervisor Operational, Fast Wakeup:

　　1.1 µA at 3.0 V (Typical)

　　Shutdown Mode (LPM4.5):

　　0.18 µA at 3.0 V (Typical)

　　Wake up From Standby Mode in 3.5 µs (Typical)

　　16-Bit RISC Architecture, Extended Memory, up to 25-MHz System Clock

　　Flexible Power-Management System

　　Fully Integrated LDO With Programmable Regulated Core Supply Voltage

　　Supply Voltage Supervision, Monitoring, and Brownout

　　Unified Clock System

　　FLL Control Loop for Frequency Stabilization

　　Low-Power Low-Frequency Internal Clock Source (VLO)

　　Low-Frequency Trimmed Internal Reference Source (REFO)

　　32-kHz Watch Crystals (XT1)

　　High-Frequency Crystals up to 32 MHz (XT2)

　　16-Bit Timer TA0, Timer_A With Five Capture/Compare Registers

　　16-Bit Timer TA1, Timer_A With Three Capture/Compare Registers

　　16-Bit Timer TA2, Timer_A With Three Capture/Compare Registers

　　16-Bit Timer TB0, Timer_B With Seven Capture/Compare Shadow Registers

　　Two Universal Serial Communication Interfaces

　　USCI_A0 and USCI_A1 Each Support:

　　Enhanced UART Supports Automatic Baud-Rate Detection

　　IrDA Encoder and Decoder

　　Synchronous SPI

　　USCI_B0 and USCI_B1 Each Support:

　　I2C

　　Synchronous SPI

　　Full-Speed Universal Serial Bus (USB)

　　Integrated USB-PHY

　　Integrated 3.3-V and 1.8-V USB Power System

　　Integrated USB-PLL

　　Eight Input and Eight Output Endpoints

　　12-Bit Analog-to-Digital Converter (ADC) (MSP430F552x Only) With Internal Reference, Sample-and-Hold, and Autoscan Feature

　　Comparator

　　Hardware Multiplier Supports 32-Bit Operations

　　Serial Onboard Programming, No External Programming Voltage Needed

　　3-Channel Internal DMA

　　Basic Timer With RTC Feature

　　Device Comparison Summarizes Available Family Members

　　TPD4S012

　　描述

　　The TPD4S012 is a four-channel Transient Voltage Suppressor (TVS) based Electrostatic Discharge (ESD) protection diode array for USB chargers and USB On-The-Go (OTG) interfaces.

　　The TPD4S012 provides IEC 61000-4-2 system level ESD Protection featuring 15 V tolerance on the VBUS line. The device is ideal for providing circuit protection for USB charger and OTG applications due to its high-voltage tolerance at the VBUS line and small flow-through package.

　　特性

　　Integrated ESD Clamps on all Pins

　　USB Signal Pins (D+, D–, ID)

　　0.8-pF Line Capacitance

　　Supports Data Rates in Excess of 480 Mbps

　　IEC 61000-4-2 ESD Protection (Level 4 Contact)

　　±10-kV IEC 61000-4-2 Contact Discharge

　　IEC 61000-4-5 Surge

　　3 Amps Peak Pulse Current

　　APPLICATIONS

　　Cellular Phones

　　Digital Cameras