原标题：大联大世平集团推出基于NXP产品的多个智能手机用智能音频功放解决方案

　　2017年7月18日，致力于亚太地区市场的领先半导体元器件分销商---大联大控股宣布，其旗下世平凭借恩智浦(NXP)产品在音响耐用性和EMC性能方面所具有的强大领先优势，推出多个基于NXP芯片的智能音频功放参考方案，力求帮助客户实现手机音质的提升，同时能够节省设计的空间。

　　大联大世平此次推出的智能手机用智能音频功放解决方案包括：

　　一、基于NXP TFA9888的单声道智能音频方案

　　二、基于NXP TFA9911的单声道智能音频方案

　　三、基于NXP TFA9896的立体声智能音频方案

　　四、基于NXP TFA9890的立体声智能音频方案

　　一、基于NXP TFA9888的智能手机用单声道智能音频方案

　　图示1-大联大世平推出基于NXP TFA9888的智能手机用单声道智能音频方案系统框架图

　　功能描述

　　① 立体声Class-D类智能音频功放

　　② 能升压到9.5V，将音量抬升

　　③ 实时侦测振幅、温度及腔体环境变化

　　④ 兼容标准声学回声消除

　　⑤ 支持混合侧音

　　重要特性

　　① 低RF敏感度

　　② 高效率和低功耗

　　③ 能极大提升音质的充足余量

　　④ 支持8kHz~48kHz的采样频率

　　⑤ 可以侦测腔体是否损坏或漏气

　　⑥ 削波抑制

　　二、基于NXP TFA9911的智能手机用单声道智能音频方案

　　图示2-大联大世平推出基于NXP TFA9911的智能手机用单声道智能音频方案系统框架图

　　功能描述

　　① 立体声Class-D类智能音频功放

　　② 能升压到9.5V，将音量抬升

　　③ 实时侦测振幅、温度及腔体环境变化

　　④ 兼容标准声学回声消除

　　⑤ 专用扬声器作为麦克风的反馈路径

　　重要特性

　　① 能极大提升音质的充足余量

　　② 支持8kHz~48kHz的采样频率

　　③ 可以侦测腔体是否损坏或漏气

　　④ 低RF敏感度

　　⑤ 削波抑制

　　三、基于NXP TFA9896的智能手机用立体声智能音频方案

　　图示3-大联大世平推出基于NXP TFA9896的智能手机用立体声智能音频方案系统框架图

　　功能描述

　　① 基于NXP TFA9896智能音频系统模块

　　② 驱动双声道喇叭工作

　　③ 支持I2S音频输入，高保真D类音频输出

　　④ 通过I2C接口对其进行控制

　　⑤ 自适应偏移控制，以保护扬声器振膜

　　重要特性

　　① 内置DSP，嵌入扬声器提升和保护算法

　　② D类放大器

　　③ 支持8kHz~48kHz的采样频率

　　④ 自适应DC-DC转换器供电

　　图示4-大联大世平推出基于NXP TFA9896的智能手机用立体声智能音频方案照片

　　四、基于NXP TFA9890的智能手机用立体声智能音频方案

　　图示5-大联大世平推出基于NXP TFA9890的智能手机用立体声智能音频方案系统框架图

　　The LPC185x/3x/2x/1x are ARM Cortex-M3 based microcontrollers for embedded applications. The ARM Cortex-M3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration.

　　The LPC185x/3x/2x/1x operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching.

　　The LPC185x/3x/2x/1x include up to 1 MB of flash and 136 kB of on-chip SRAM, 16 kB of EEPROM memory, a quad SPI Flash Interface (SPIFI), a State Configurable Timer (SCT) subsystem, two High-speed USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals.

　　特性

　　Processor core

　　ARM Cortex-M3 processor, running at CPU frequencies of up to 180 MHz

　　ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions

　　ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC)

　　Non-maskable Interrupt (NMI) input

　　JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points

　　Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support

　　System tick timer

　　On-chip memory

　　Up to 1 MB on-chip dual bank flash memory with flash accelerator

　　16 kB on-chip EEPROM data memory

　　136 kB SRAM for code and data use

　　Multiple SRAM blocks with separate bus access

　　64 kB ROM containing boot code and on-chip software drivers

　　64 bit of One-Time Programmable (OTP) memory for general-purpose use

　　Clock generation unit

　　Crystal oscillator with an operating range of 1 MHz to 25 MHz

　　12 MHz internal RC oscillator trimmed to 2 % accuracy over temperature and voltage (1 % accuracy for Tamb = 0 °C to 85 °C)

　　Ultra-low power RTC crystal oscillator

　　Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. The second PLL can be used with the High-speed USB, the third PLL can be used as audio PLL

　　Clock output

　　Configurable digital peripherals

　　State Configurable Timer (SCT) subsystem on AHB

　　Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like timers, SCT, and ADC0/1

　　Serial interfaces

　　Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 52 MB per second

　　10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2)

　　One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY (USB0)

　　One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to an external high-speed PHY (USB1)

　　USB interface electrical test software included in ROM USB stack

　　Four 550 UARTs with DMA support: one UART with full modem interface; one UART with IrDA interface; three USARTs support UART synchronous mode and a smart card interface conforming to ISO7816 specification

　　Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller excludes operation of all other peripherals connected to the same bus bridge

　　Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support

　　One Fast-mode Plus I²C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I²C-bus specification. Supports data rates of up to 1 Mbit/s

　　One standard I²C-bus interface with monitor mode and standard I/O pins

　　Two I²S interfaces with DMA support, each with one input and one output

　　Digital peripherals

　　External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices

　　LCD controller with DMA support and a programmable display resolution of up to 1024H x 768V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel mapping

　　SD/MMC card interface

　　Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB slaves

　　Up to 164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors

　　GPIO registers are located on the AHB for fast access. GPIO ports have DMA support

　　Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources

　　Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins

　　Four general-purpose timer/counters with capture and match capabilities

　　One motor control PWM for three-phase motor control

　　One Quadrature Encoder Interface (QEI)

　　Repetitive Interrupt timer (RI timer)

　　Windowed watchdog timer

　　Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes of battery powered backup registers

　　Event recorder with three inputs to record event identification and event time; can be battery powered

　　Alarm timer; can be battery powered

　　Analog peripherals

　　One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s

　　Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s. Up to eight analog channels total. Each analog input is connected to both ADCs

　　Unique ID for each device

　　Power

　　Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for the core supply and the RTC power domain

　　RTC power domain can be powered separately by a 3 V battery supply

　　Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down

　　Processor wake-up from Sleep mode via wake-up interrupts from various peripherals

　　Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain

　　Brownout detect with four separate thresholds for interrupt and forced reset

　　Power-On Reset (POR)

　　Available in LQFP208, LBGA256, LQFP144, and TFBGA100 packages

　　Target Applications

　　Industrial

　　Consumer

　　White goods

　　RFID readers

　　e-Metering

　　功能描述

　　① 基于NXP TFA9890智能音频系统评估板

　　② 驱动左右声道喇叭工作

　　③ 支持I2S音频输入，高保真D类音频输出

　　④ 通过I2C接口对其进行控制

　　⑤ 自适应偏移控制，以保护扬声器隔膜

　　重要特性

　　① 内置DSP, 嵌入扬声器提升和保护算法

　　② D类放大器, 输出功率2.65W

　　③ 支持8kHz~48kHz的采样频率

　　④ 自适应DC-DC转换器供电

　　图示6-大联大世平推出基于NXP TFA9890的智能手机用立体声智能音频方案照片

　　The TFA9890A is a high efficiency class-D audio amplifier with a sophisticated speaker boost and protection algorithm. It can deliver 7.2 W peak output power into an 8 Ω speaker at a supply voltage of 3.6 V. The internal boost converter raises the supply voltage to 9.5 V, providing ample headroom for major improvements in sound quality.

　　A safe working environment is provided for the speaker under all operating conditions. The TFA9890A maximizes acoustic output while ensuring diaphragm displacement and voice coil temperature do not exceed their rated limits. This function is based on a speaker box model that operates in all loudspeaker environments (e.g. free air, closed box or vented box). Furthermore, advanced signal processing ensures that the quality of the audio signal is never degraded by unwanted clipping or distortion in the amplifier or speaker.

　　Unlike competing solutions, the adaptive sound maximizer algorithm uses feedback to accurately calculate both the temperature and the excursion, allowing the TFA9890A to adapt to changes in the acoustic environment.

　　Internal intelligent DC-to-DC conversion boosts the supply rail to provide additional headroom and power output. The supply voltage is only raised when necessary. This maximizes the output power of the class-D audio amplifier while limiting quiescent power consumption.

　　The TFA9890A also incorporates advanced battery protection. By limiting the supply current when the battery voltage is low, it prevents the audio system from drawing excessive load currents from the battery, which could cause a system undervoltage. The advanced processor minimizes the impact of a falling battery voltage on the audio quality by preventing distortion as the battery discharges.

　　The device features low RF susceptibility because it has a digital input interface that is insensitive to clock jitter. The second order closed loop architecture used in a class-D audio amplifier provides excellent audio performance and high supply voltage ripple rejection. The audio input interface is I²S and the control settings are communicated via an I²C-bus interface.

　　The device also provides the speaker with robust protection against ESD damage. In a typical application, no additional components are needed to withstand a 15 kV discharge on the speaker.

　　The TFA9890A is available in a 49-bump WLCSP (Wafer Level Chip-Size Package) with a 400 μm pitch.