NXP S32V234视频处理器开发方案
The S32V234 is our 2nd generation vision processor family designed to support computation intensive applications for image processing and offers an ISP, powerful 3D GPU, dual APEX-2 vision accelerators, security and supports SafeAssure™.S32V234 is suited for ADAS, NCAP front camera, object detection and recognition, surround view, machine learning and sensor fusion applications. S32V234 is engineered for automotive-grade reliability, functional safety and security measures to support vehicle and industrial automation.
S32V234 has a complete enablement platform supported by S32 Design Studio IDE for Vision which includes a compiler, debugger, Vision SDK, Linux BSP and graph tools.
S32V234主要特性:
• ARM Cortex-A53, 64-bit CPU
– Up to 1000 MHz Quad ARM Cortex-A53
– 32 KB/32 KB I-/D- L1 Cache
– NEON MPE co-processor
– Dual precision FPU
– 2 clusters with 2 CPUs and 256 KB L2 cache each
– Memory Management Unit
– GIC Interrupt Controller
– ECC/parity error support for its memories
– Generic timers
– Fault encapsulation by hardware for redundantexecuted application software on multiple corecluster
• ARM Cortex-M4, 32-bit CPU
– Up to 133 MHz
– 16 KB/16 KB I-/D- L1 Cache
– 32+32 KB tightly coupled memory (TCM)
– ECC/parity support for its memories
• Clocks
– Phase Locked Loops (PLLs)
– 1 external crystal oscillator (FXOSC)
– 1 FIRC oscillator
• System protection and power management features
– Flexible run modes to consume low power based onapplication needs
– Peripheral clock enable register can disable clocks tounused modules, thereby reducing currents
– Power gating of unused A53 cores and GPU
– Low and high voltage warning and detect
– Hardware CRC module to support fast cyclicredundancy checks (CRC)
– 120-bit unique chip identifier
– Hardware watchdog
– eDMA controller with 32 channels (withDMAMUX)
– Extended Resource Domain Controller
• Safety concept
– ISO 26262, ASIL level target
– Measures to detect faults in memory and logic
– Measures to detect single point and latent faults
– Quantitative out of context analysis of functionalsafety (FMEDA) tailored to application specifics
– Safety manual and FMEDA report available
• Security
– CSE with 16 KB of on-chip Secure RAM and ROM.
– ARM TrustZone (TZ) architecture support
– Boot from NOR flash with AES-128 (CTR)
– On-Chip One-Time Programmable elementController (OCOTP_CTRL) with on chip electricalfuse array.
– System JTAG Controller (SJC)
• Debug functionality
– Standard JTAG and Compact JTAG
– 16-bit Trace port, Serial Wire Output port
• Timers
– General purpose timers (FTM)
– Two Periodic Interrupt Timer (PIT)
– IEEE 1588 Timers (part of Ethernet Subsystem)
• Analog
– 1x 12-bit 1.8 V SAR ADC with self-test
• Communications
– UART(w/ LIN2.1l)
– Serial peripheral interface (SPI)
– I2C blocks
– PCI express 2.0 with endpoint and root complexsupport
– LFAST serial link
– 1 GBit Ethernet with PTP IEEE 1588
– FD-CAN
– FlexRay Dual Channel, Version 2.1 RevA
• Memory interfaces
– 32-bit DRAM Controller with support for LPDDR2/DDR3/DDR3L - Up to 1066 MHz data rate with ECC (SEC-DEDTED)triple errror detection support for subregion
– QuadSPI supporting Execute-In-Place (XIP)
– Boot flash fault detection and correction using two-dimensional parity.
– Triple fault detection and single fault correction scheme for external DDR-RAM including address/page fault detection.
• Video input interfaces, Image processing, graphics processing, display
– Display Control Unit (2D-ACE) with 24-bit RGB, GPU frame buffer decoding
– GPU GC3000 with frame buffer compression
– 2x VIU (Video interface unit) for camera input
– 2x MIPICSI2 with four lanes for camera input (support 1080 pixel @ 30 fps)
– Image signal processor (ISP), supporting 2x1 or 1x2 megapixel @ 30 fps and 4x2 megapixel for subset of functions(exposure control, gamma correction)
– 2x APEX2-CL Image cognition processor supporting OpenCL 1.2. APEX-642CL comprises two Array Processing Unit
(APU) cores configurable as single SIMD engine with 64 16-bit Computational Units (CU), or configurable as two coreMIMD engines with 32 16-bit CUs each.
– CUs are comprised of four Functional Units: 16-bit Multiplier, Load Store Unit, ALU, and Shifter
– JPEG video decoder (8/12-bit)
– H.264 video decoder (8/10/12-bit), High-intra and constrained baseline formats
– H.264 video encode (8/10/12-bit), High-intra only
– Fast DMA for data transfers between DRAM and System RAM with CRC
• Human-Machine Interface (HMI)
– GPIO pins with interrupt support, DMA request capability, digital glitch filter
– Configurable slew rate and drive strength on all output pins
• System RAM
– 4 MB On-Chip System RAM with ECC
S32V234目标应用:
Automotive
Front View Camera
Smart Rear View Camera
Surround View & Sense Park Assist System
Surround View Park Assist System
图1.S32V234框图
评估板SBC-S32V234
SBC-S32V234: S32V234 Vision and Sensor Fusion Evaluation Board for Prototyping and Development
图2.评估板SBC-S32V234 CRX-S32V载体板框图
图3.评估板SBC-S32V234 MPX-S32V模块框图
图4.评估板SBC-S32V234外形图
图5.评估板SBC-S32V234模块边连接器(载体板CRX-S32V)外形图
图6.评估板SBC-S32V234非模块边连接器(载体板CRX-S32V)外形图
图7.评估板SBC-S32V234模块(MPX-S32V)外形图(正面)
图8.评估板SBC-S32V234模块(MPX-S32V)外形图(背面)
评估板SBC-S32V234主要特性:
图9.评估板SBC-S32V234电路图(1)
图10.评估板SBC-S32V234电路图(2)
图11.评估板SBC-S32V234电路图(3)
图12.评估板SBC-S32V234电路图(4)
图13.评估板SBC-S32V234电路图(5)
图14.评估板SBC-S32V234电路图(6)
图15.评估板SBC-S32V234电路图(7)
图16.评估板SBC-S32V234电路图(8)
图17.评估板SBC-S32V234电路图(9)
图18.评估板SBC-S32V234电路图(10)
图19.评估板SBC-S32V234电路图(11)
图20.评估板SBC-S32V234电路图(12)
图21.评估板SBC-S32V234电路图(13)
NXP (恩智浦半导体)是一家新近独立的半导体公司,由飞利浦公司创立,已拥有五十年的悠久历史,主要提供工程师与设计人员各种半导体产品与软件,为移动通信、消费类电子、安全应用、非接触式付费与连线,以及车内娱乐与网络等产品带来更优质的感知体验。
2016年10月28日,高通收购荷兰半导体商NXP 涉资470亿美元。[1]
2015年2月,飞思卡尔与 NXP达成合并协议,合并后整体市值 400 亿美金。收购在2015年下半年彻底完成。
凭借对消费者长期累积的调查研究、各项庞大的研发投资与世界级的合作伙伴,NXP 的生动体验“芯”技术 (vibrant media technology) 能让消费者享受到更好的感知体验,例如色彩鲜明的图像、清晰响亮的声音,以及在家中、车上与移动设备上轻松分享各种信息等。
恩智浦半导体 以其领先的射频、模拟、电源管理、接口、安全和数字处理方面的专长,提供高性能混合信号(High Performance Mixed Signal)和标准产品解决方案。这些创新的产品和解决方案可广泛应用于汽车、智能识别、无线基础设施、照明、工业、移动、消费和计算等领域。公司在全球逾25个国家都设有业务执行机构,2013年公司净收入达到48.2亿美元。
详情请见:
责任编辑:Davia
【免责声明】
1、本文内容、数据、图表等来源于网络引用或其他公开资料,版权归属原作者、原发表出处。若版权所有方对本文的引用持有异议,请联系拍明芯城(marketing@iczoom.com),本方将及时处理。
2、本文的引用仅供读者交流学习使用,不涉及商业目的。
3、本文内容仅代表作者观点,拍明芯城不对内容的准确性、可靠性或完整性提供明示或暗示的保证。读者阅读本文后做出的决定或行为,是基于自主意愿和独立判断做出的,请读者明确相关结果。
4、如需转载本方拥有版权的文章,请联系拍明芯城(marketing@iczoom.com)注明“转载原因”。未经允许私自转载拍明芯城将保留追究其法律责任的权利。
拍明芯城拥有对此声明的最终解释权。