原标题：NXP DAC1008D750双路750MSPS数模转换方案

　　nxp公司的DAC1008D750是集成了JESD204A接口的双路10位750MSPS数模转换器, 可选择2/4/8内插滤波器以优化多载波WCDMA发送器,IMD3为80 dBc, fs = 737.28 Msps而fo = 140 MHz,最大速率为750MSPS,双载波WCDMA的ACPR为64dBc,主要用在无线基础架构如LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA;LMDS/MIMO和点对点通信,直接数字合成(DDS),宽带无线系统,数字无线链路以及自动测试设备(ATE)和仪表.本文介绍了 DAC1008D750主要特性和优势,方框图以及ESD204A接收器, 主从模式框图和全从模式框图.

　　DAC1008D750:Dual 10-bit DAC; up to 750 Msps; 2,4 or 8 interpolating with JESD204A interface

　　The DAC1008D750 is a high-speed 10-bit dual channel Digital-to-Analog Converter

　　(DAC) with selectable 2,4or 8 interpolating filters optimized for multi-carrier WCDMA transmitters.

　　Because of its digital on-chip modulation, the DAC1008D750 allows the complex pattern provided through lane 0, lane 1, lane 2 and lane 3, to be converted up from baseband to IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register.

　　The DAC1008D750 also includes a 2,4or 8 clock multiplier which provides the appropriate internal clocks and an internal regulation to adjust the output full-scale current.

　　The input data format is serial according to JESD204A specification. This new interface has numerous advantages over the traditional parallel one: easy PCB layout, lower radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum number of lanes of the DAC1008D750 is 4 and its maximum serial data rate is 3.125 Gbps.

　　The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output clock period between several DAC devices. MDS incorporates modes: Master/slave and All slave mode.

　　DAC1008D750主要特性和优势:

　　Dual 10-bit resolution

　　IMD3: 80 dBc; fs = 737.28 Msps; fo = 140 MHz

　　750 Msps maximum update rate

　　ACPR: 64 dBc; two carriers WCDMA;

　　fs = 737.28 Msps; fo = 153.6 MHz

　　Selectable 2,4or 8interpolation filters

　　Typical 1.26 W power dissipation at 4interpolation, PLL off and 740 Msps

　　Input data rate up to 312.5 Msps

　　Power-down mode and Sleep modes

　　Very low-noise cap-free integrated PLL

　　Differential scalable output current from 1.6 mA to 22 mA

　　32-bit programmable NCO frequency

　　On-chip 1.25 V reference

　　Four JESD204A serial input lanes

　　External analog offset control

　　(10-bit auxiliary DACs)

　　1.8 V and 3.3 V power supplies

　　Internal digital offset control

　　LVDS compatible clock inputs

　　Inverse (sin x) / x function

　　Two’s complement or binary offset data format

　　Fully compatible SPI port

　　LMF = 421 or LMF = 211 support

　　Industrial temperature range from −40 C to +85 C

　　Differential CML receiver with embedded termination

　　Integrated PLL can be bypassed

　　Synchronization of multiple DAC outputs

　　Embedded complex modulator

　　DAC1008D750应用:

　　Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA

　　Communication: LMDS/MMDS, point-to-point

　　Direct Digital Synthesis (DDS)

　　Broadband wireless systems

　　Digital radio links

　　Instrumentation

　　Automated Test Equipment (ATE)

　　图1.DAC1008D750方框图

　　图2.DAC1008D750 JESD204A接收器

　　图3.DAC1008D750主从模式框图

　　图4.DAC1008D750全从模式框图