原标题：Freescale I.MX535多媒体应用处理器开发方案

　　freescale公司的I.MX535是最新的多媒体应用处理器,采用ARM内核,时钟速率高达1.2GHz,能和DDR2/LVDDR2-800, LPDDR2-800或DDR3-800 DRAM存储器接口,具有HD视频功能,提供最高的处理性能和有业界最低的功耗,主要用在平板电脑,高端MID,智能电子书,多媒体手机,PMP,游戏机,互联网监视器等.本文介绍了I.MX53xD处理器和多媒体应用处理器主要特性,方框图,以及I.MX53 QS开发板主要特性,方框图,详细电路图和所用材料清单.

　　The i.MX53xD multimedia applications processors are Freescale Semiconductor’s latest addition to a growing family of multimedia-focused products offering high performance processing optimized for lowest power consumption.

　　The i.MX53xD processor features Freescale’s advanced implementation of the ARM™ core, which operates at clock speeds as high as 1.2 GHz and interfaces with DDR2/LVDDR2-800, LPDDR2-800, or DDR3-800 DRAM memories. This device is suitable for applications such as the following:

　　• Tablets, High-end mobile internet devices (MID)

　　• Smartbooks

　　• Thin clients

　　• Internet Monitors, Media Phones, High-end portable media players (PMP) with HD video capability

　　• Gaming consoles

　　The flexibility of the i.MX53xD architecture allows for its use in a wide variety of applications. As the heart ofthe application chipset, the i.MX53xD processor provides all the interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, hard drive, camera sensors, and dual displays.

　　I.MX53xD处理器主要特性:

　　Features of the i.MX53xD processor include the following:

　　• Applications processor—The i.MX53xD processors boost the capabilities of high-tier portable applications by satisfying the ever increasing MIPS needs of operating systems and games.

　　Freescale’s Dynamic Voltage and frequency Scaling (DVFS) provides significant power reduction, allowing the device to run at lower voltage and frequency with sufficient MIPS for tasks such as audio decode.

　　• Multilevel memory system—The multilevel memory system of the i.MX53xD is based on the L1 instruction and data caches, L2 cache, internal and external memory. The i.MX53xD supports many types of external memory devices, including DDR2, low voltage DDR2, LPDDR2, DDR3, NOR Flash, PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed NAND including eMMC up to rev 4.4.

　　• Smart speed technology—The i.MX53xD device has power management throughout the IC that enables the rich suite of multimedia features and peripherals to consume minimum power in both active and various low power modes. Smart Speed Technology enables the designer to deliver a feature-rich product requiring levels of power far lower than industry expectations.

　　• Multimedia powerhouse—The multimedia performance of the i.MX53xD processor ARM core is boosted by a multilevel cache system, Neon (including advanced SIMD, 32-bit single-precision floating point support) and vector floating point coprocessors. The system is further enhanced by a multistandard hardware video codec, autonomous image processing unit (IPU), SD and HD720p triple video (TV) encoder with triple video DAC, and a programmable smart DMA (SDMA) controller.

　　• Powerful graphics acceleration—Graphics is the key to mobile game, navigation, web browsing, and other applications. The i.MX53xD processors provide two independent, integrated graphics processing units: an OpenGL® ES 2.0 3D graphics accelerator (33 Mtri/s, 200 Mpix/s, and 800 Mpix/s z-plane performance) and an OpenVG™ 1.1 2D graphics accelerator (200 Mpix/s).

　　• Interface flexibility—The i.MX53xD processor supports connection to a variety of interfaces, including LCD controller for two displays and CMOS sensor interface, high-speed USB on-the-go with PHY, plus three high-speed USB hosts, multiple expansion card ports (high-speed MMC/SDIO host and other), 10/100 Ethernet controller, and a variety of other popular interfaces (PATA, UART, I2C, and I2S serial audio, among others).

　　• Automotive environment support—Includes interfaces such as two CAN ports, an ESAI audio interface, and an asynchronous sample rate converter for multichannel/multisource audio.

　　• Advanced security—The i.MX53xD processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption, secure boot, and secure software downloads. For detailed information about the i.MX53xD security features contact a Freescale representative.

　　The i.MX53xD application processor is a follow-on to the i.MX51, with improved performance, power efficiency, and multimedia capabilities.

　　I.MX53xD多媒体应用处理器主要特性:

　　The i.MX53xD multimedia applications processor (AP) is based on the ARM Platform, which has the following features:

　　• MMU, L1 instruction and L1 data cache

　　• Unified L2 cache

　　• Target frequency of the core (including Neon, VFPv3 and L1 cache): 1 GHz

　　• Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite) coprocessor supporting VFPv3

　　• TrustZone

　　The memory system consists of the following components:

　　• Level 1 cache:

　　— Instruction (32 Kbyte)

　　— Data (32 Kbyte)

　　• Level 2 cache:

　　— Unified instruction and data (256 Kbyte)

　　• Level 2 (internal) memory:

　　— Boot ROM, including HAB (64 Kbyte)

　　— Internal multimedia/shared, fast access RAM (128 Kbyte)

　　— Secure/non-secure RAM (16 Kbyte)

　　• External memory interfaces:

　　— 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte

　　— 32bit LPDDR2

　　— 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC 8,16-bit NOR Flash, PSRAM & cellular RAM.32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM.

　　— 8-bit Asynchronous (DTACK mode) EIM interface.

　　— All EIM pins are muxed on other interfaces (data with NFC pins). I/O muxing logic selects EIM port, as primary muxing at system boot.

　　— Samsung OneNAND™ and managed NAND including eMMC up to rev 4.4 (in muxed I/O mode)

　　The i.MX53xD system is built around the following system on chip interfaces:

　　• 64-bit AMBA AXI v1.0 bus—used by ARM platform, multimedia accelerators (such as VPU, IPU, GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz.

　　• 32-bit AMBA AHB 2.0 bus—used by the rest of the bus master peripherals operating at 133 MHz.

　　• 32-bit IP bus—peripheral bus used for control (and slow data traffic) of the most system peripheral devices operating at 66 MHz.

　　The i.MX53xD makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia performance. The use of hardware accelerators provides both high performance and low power consumption while freeing up the CPU core for other tasks.

　　The i.MX53xD incorporates the following hardware accelerators:

　　• VPU, version 3—video processing unit

　　• GPU3D—3D graphics processing unit, OpenGL ES 2.0, version 3, 33 Mtri/s, 200 Mpix/s, and 800 Mpix/s z-plane performance, 256 Kbyte RAM memory

　　• GPU2D—2D graphics accelerator, OpenVG 1.1, version 1, 200 Mpix/s performance,

　　• IPU, version 3M—image processing unit

　　• ASRC—asynchronous sample rate converter

　　The i.MX53xD includes the following interfaces to external devices:

　　• Hard disk drives:

　　— PATA, up to U-DMA mode 5, 100 MByte/s

　　— SATA I, 1.5 Gbps

　　• Displays:

　　— Five interfaces available. Total rate of all interfaces is up to 180 Mpixels/s, 24 bpp. Up to two interfaces may be active at once.

　　— Two parallel 24-bit display ports. The primary port is up to 165 Mpix/s (for example,UXGA @ 60 Hz).

　　LVDS serial ports: one dual channel port up to 165 Mpix/s or two independent single channel ports up to 85 MP/s (for example, WXGA @ 60 Hz) each.

　　— TV-out/VGA port up to 150 Mpix/s (for example, 1080p60).

　　• Camera sensors:

　　— Two parallel 20-bit camera ports. Primary up to 180-MHz peak clock frequency, secondary up to 120-MHz peak clock frequency.

　　• Expansion cards:

　　— Four SD/MMC card ports: three supporting 416 Mbps (8-bit i/f) and one enhanced port supporting 832 Mbps (8-bit, eMMC 4.4).

　　• USB

　　— High-speed (HS) USB 2.0 OTG (up to 480 Mbps), with integrated HS USB PHY

　　— Three USB 2.0 (480 Mbps) hosts:

　　– High-speed host with integrated on-chip high-speed PHY

　　– Two high-speed hosts for external HS/FS transceivers through ULPI/serial, support IC-USB

　　• Miscellaneous interfaces:

　　— One-wire (OWIRE) port

　　— Three I2S/SSI/AC97ports, supporting up to 1.4 Mbps, each connected to audio multiplexer (AUDMUX) providing four external ports.Five UART RS232 ports, up to 4.0 Mbps each. One supports 8-wire, the other four support 4-wire.

　　— Two high speed enhanced CSPI (ECSPI) ports plus one CSPI port

　　— Three I2C ports, supporting 400 kbps

　　— Fast Ethernet controller, IEEE1588 V1 compliant, 10/100 Mbps

　　— Two controller area network (FlexCAN) interfaces, 1 Mbps each

　　— Sony Phillips Digital Interface (SPDIF), Rx and Tx

　　— Enhanced serial audio interface (ESAI), up to 1.4 Mbps each channel

　　— Key pad port (KPP)

　　— Two pulse-width modulators (PWM)

　　— GPIO with interrupt capabilities

　　— Secure JTAG controller (SJC)

　　The system supports efficient and smart power control and clocking:

　　• Supporting DVFS (dynamic voltage and frequency scaling) technique for low power modes

　　• Power gating SRPG (State Retention Power Gating) for ARM core and Neon

　　• Support for various levels of system power modes

　　• Flexible clock gating control scheme

　　• On-chip temperature monitor

　　• On-chip oscillator amplifier supporting 32.768 kHz external crystal

　　• On-chip LDO voltage regulators for PLLs Security functions are enabled and accelerated by the following hardware:

　　• ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so on)

　　• Secure JTAG controller (SJC)—Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features

　　• Secure real-time clock (SRTC)—Tamper resistant RTC with dedicated power domain and mechanism to detect voltage and clock glitches

　　• Real-time integrity checker, version 3 (RTICv3)—RTIC type1, enhanced with SHA-256 engine

　　• SAHARAv4 Lite—Cryptographic accelerator that includes true random number generator (TRNG)

　　• Security controller, version 2 (SCCv2)—Improved SCC with AES engine, secure/non-secure RAM and support for multiple keys as well as TZ/non-TZ separation

　　• Central security unit (CSU)—Enhancement for the IIM (IC Identification Module). CSU is configured during boot by e-fuses, and determines the security level operation mode as well as the TrustZone (TZ) policy

　　• Advanced High Assurance Boot (A-HAB)—HAB with the next embedded enhancements:SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization

　　图1.i.MX53xD系统方框图

　　I.MX53 QS开发板

　　i.MX53 Quick Start Development Board

　　The Quick Start Board is an i.MX535 platform designed to showcase many of the most commonly used features of the i.MX535 Applications Processor in a small, low cost package. The MCIMX53-START is an entry level development board and a near perfect subset of its larger sister board, the MCIMX53SMD, which is available as a full, near-form factor tablet. Developers can start working with code on the Quick Start board, and then port it over to the SMD Tablet if additional features are desired. This gives the developer the option of becoming familiar with the i.MX535 Applications Processor before investing a large amount or resources in more specific designs.

　　I.MX53 QS开发板主要特性:

　　Features of the i.MX53 Quick Start board are:

　　Processor: Freescale Applications Processor MCIMX535DVV1B

　　DRAM Memory: Micron 8Gb DDR3 SDRAM MT41J128M16HA-187E:D

　　PMIC: Dialog Semiconductor DA9053

　　Mass Storage: 5 in 1 SD/MMC/SDIO Card Connector

　　microSD Card Connector

　　7-pin SATA Data Connector

　　Video Output: 15-Pin D-Sub VGA Connector

　　30-Pin LVDS Connector

　　Ethernet: RJ-45 Connector for 10/100 Base-T

　　USB: Dedicated HS USB 2.0 Standard-A Host Connector

　　Shared HS USB 2.0 Standard - Host and Micro-B Device Connectors

　　Audio Connectors: 3.5mm Stereo Head Phone output

　　3.5mm Mono-Microphone input and Mono Head Phone (right channel) output

　　Power Connectors: 5V mm Barrel Connector

　　Debug Connectors: 9-Pin D-Sub Debug UART Connector

　　20-Pin Standard ARM JTAG Connector

　　Expansion Header: 120-Pin Header (Populated) to Support 1 of the following:

　　Optional HDMI Output Daughter Card (orderable)

　　Optional WVGA and WQVGA LCD Display Daughter Cards (orderable)

　　Camera Daughter Card (custom)

　　SDIO Based WiFi Daughter card (custom)

　　User Interface Buttons: Power, Reset, 2 User-Defined Buttons

　　Indicators: 8 Status LEDs – External Power, PMIC ON, Fault Condition, and more

　　Li-ION Battery Connector: 3-Pin Header (unpopulated) for Li-ION Battery for Low Power Operation

　　Coin Cell: Connection point for 2-Pin Coin Cell (unpopulated) for RTC Operation

　　PCB: 3.0 inch x 3.0 inch (76.2 mm x 76.2 mm), 10 - layer board

　　I.MX53 QS开发板包括:

　　i.MX53 Quick Start Development Board Kit Contents

　　• i.MX53 1 GHz ARM Cortex-A8 processor

　　• 4 GB microSD card with Linux image

　　• 5V power supply with worldwide adapters

　　• Micro USB cable

　　• Quick Start Guide

　　• DVD with VMware player, getting started video, demos and other documents

　　图2.I.MX53 QS开发板外形图

　　I.MX53 QS开发板硬件主要特性:

　　图3.I.MX53 QS开发板方框图

　　I.MX53 QS开发板材料清单(BOM):