原标题：TI-LM3S8962-Ethernet+CAN 的解决方案

　　TI的Stellaris LM3S8000系列基于ARM Cortex-M3 的 MCU.控制器局域网(CAN)与ARM架构MCU中的全面集成,以太网解决方案完美结合. .本文介绍了LM3S8962主要特性,框图,典型应用电路。

　　Stellaris 基于实现了革命性突破的 ARM® Cortex™-M3 技术之上，是业界领先的高可靠性实时微处理器 (MCU) 产品系列。获奖的 Stellaris 32 位 MCU 将先进灵活的混合信号片上系统集成优势同无与伦比的实时多任务功能进行了完美结合。功能强大、编程便捷的低成本 Stellaris MCU 现在可轻松实现此前使用原有 MCU 所无法实现的复杂应用。Stellaris 系列拥有 160 多种产品，可提供业界最广泛的精确兼容型 MCU 供选择。

　　Stellaris 系列面向需要高级控制处理与连接功能的低成本应用，如运动控制、监控(远程监控、消防/安防监控等)、HVAC 与楼宇控制、电源与能量监控与转换、网络设备与交换机、工厂自动化、电子销售点设备、测量测试设备、医疗仪表以及游戏设备等。Stellaris MCU 广泛用于全世界的许多工业和产品中，包括运动控制、工业自动化、医疗、运输、设备以及安全性和访问。

　　TI 公司的Stellaris® 系列实施了业界首个最全面的 Cortex-M3 和 Thumb-2 指令集。具有令人惊叹的快速响应能力，Thumb-2 技术将 16 位和 32 位指令相结合，使代码密度和性能达到了最佳平衡。Thumb-2 比纯 32 位代码使用的内存要少 26%，从而降低了系统成本，同时将性能提高了 25%。

　　Stellaris MCU 和 ARM Cortex-M3 使开发人员能够直接使用业界最强大的开发工具、软件和知识系统。新型 Stellaris MCU 包含用于运动控制应用的唯一 IP、智能模拟功能和高级扩展连接选项，可以为工业应用提供各种高性价比的解决方案。除了经配置后可用于通用实时系统的 MCU 之外，Stellaris系列还可针对下列各种应用提供功能独特的解决方案，如高级运动控制与能源转换应用、实时网络与实时网络互连，以及包括互连运动控制与硬实时联网等在内的上述应用的组合。

　　The LM3S8962 microcontroller 技术亮点

　　■ 32-Bit RISC Performance

　　– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications

　　– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism

　　– Thumb®-compatible Thumb-2-only instruction set processor core for high code density

　　– 50-MHz operation

　　– Hardware-division and single-cycle-multiplication

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　　– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling

　　– 36 interrupts with eight priority levels

　　– Memory protection unit (MPU), providing a privileged mode for protected operating system functionality

　　– Unaligned data access, enabling data to be efficiently packed into memory

　　– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control

　　■ ARM® Cortex™-M3 Processor Core

　　– Compact core.

　　– Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications.

　　– Rapid application execution through Harvard architecture characterized by separate buses for instruction and data.

　　– Exceptional interrupt handling, by implementing the register manipulations required for handling

　　an interrupt in hardware.

　　– Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining

　　– Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.

　　– Migration from the ARM7™ processor family for better performance and power efficiency.

　　– Full-featured debug solution

　　• Serial Wire JTAG Debug Port (SWJ-DP)

　　• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints

　　• Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,and system profiling

　　• Instrumentation Trace Macrocell (ITM) for support of printf style debugging

　　• Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer

　　– Optimized for single-cycle flash usage

　　– Three sleep modes with clock gating for low power

　　– Single-cycle multiply instruction and hardware divide

　　– Atomic operations

　　– ARM Thumb2 mixed 16-/32-bit instruction set

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　　Architectural Overview

　　– 1.25 DMIPS/MHz

　　■ JTAG

　　– IEEE 1149.1-1990 compatible Test Access Port (TAP) controller

　　– Four-bit Instruction Register (IR) chain for storing JTAG instructions

　　– IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST

　　– ARM additional instructions: APACC, DPACC and ABORT

　　– Integrated ARM Serial Wire Debug (SWD)

　　■ Hibernation

　　– System power control using discrete external regulator

　　– Dedicated pin for waking from an external signal

　　– Low-battery detection, signaling, and interrupt generation

　　– 32-bit real-time clock (RTC)

　　– Two 32-bit RTC match registers for timed wake-up and interrupt generation

　　– Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal

　　– RTC predivider trim for making fine adjustments to the clock rate

　　– 64 32-bit words of non-volatile memory

　　– Programmable interrupts for RTC match, external wake, and low battery events

　　■ Internal Memory

　　– 256 KB single-cycle flash

　　• User-managed flash block protection on a 2-KB block basis

　　• User-managed flash data programming

　　• User-defined and managed flash-protection block

　　– 64 KB single-cycle SRAM

　　■ GPIOs

　　– 5-42 GPIOs, depending on configuration

　　– 5-V-tolerant in input configuration

　　– Fast toggle capable of a change every two clock cycles

　　– Programmable control for GPIO interrupts

　　• Interrupt generation masking

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　　• Edge-triggered on rising, falling, or both

　　• Level-sensitive on High or Low values

　　– Bit masking in both read and write operations through address lines

　　– Can initiate an ADC sample sequence

　　– Pins configured as digital inputs are Schmitt-triggered.

　　– Programmable control for GPIO pad configuration

　　• Weak pull-up or pull-down resistors

　　• 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can be configured with an 18-mA pad drive for high-current applications

　　• Slew rate control for the 8-mA drive

　　• Open drain enables

　　• Digital input enables

　　■ General-Purpose Timers

　　– Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters. Each GPTM can be configured to operate independently:

　　• As a single 32-bit timer

　　• As one 32-bit Real-Time Clock (RTC) to event capture

　　• For Pulse Width Modulation (PWM)

　　• To trigger analog-to-digital conversions

　　– 32-bit Timer modes

　　• Programmable one-shot timer

　　• Programmable periodic timer

　　• Real-Time Clock when using an external 32.768-KHz clock as the input

　　• User-enabled stalling when the controller asserts CPU Halt flag during debug

　　• ADC event trigger

　　– 16-bit Timer modes

　　• General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only)

　　• Programmable one-shot timer

　　• Programmable periodic timer

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　　Architectural Overview

　　• User-enabled stalling when the controller asserts CPU Halt flag during debug

　　• ADC event trigger

　　– 16-bit Input Capture modes

　　• Input edge count capture

　　• Input edge time capture

　　– 16-bit PWM mode

　　• Simple PWM mode with software-programmable output inversion of the PWM signal

　　■ ARM FiRM-compliant Watchdog Timer

　　– 32-bit down counter with a programmable load register

　　– Separate watchdog clock with an enable

　　– Programmable interrupt generation logic with interrupt masking

　　– Lock register protection from runaway software

　　– Reset generation logic with an enable/disable

　　– User-enabled stalling when the controller asserts the CPU Halt flag during debug

　　■ ADC

　　– Four analog input channels

　　– Single-ended and differential-input configurations

　　– On-chip internal temperature sensor

　　– Sample rate of 500 thousand samples/second

　　– Flexible, configurable analog-to-digital conversion

　　– Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs

　　– Flexible trigger control

　　• Controller (software)

　　• Timers

　　• Analog Comparators

　　• PWM

　　• GPIO

　　– Hardware averaging of up to 64 samples for improved accuracy

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　　– Converter uses an internal 3-V reference

　　– Power and ground for the analog circuitry is separate from the digital power and ground

　　■ UART

　　– Two fully programmable 16C550-type UARTs with IrDA support

　　– Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading

　　– Programmable baud-rate generator allowing speeds up to 3.125 Mbps

　　– Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface

　　– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8

　　– Standard asynchronous communication bits for start, stop, and parity

　　– Line-break generation and detection

　　– Fully programmable serial interface characteristics

　　• 5, 6, 7, or 8 data bits

　　• Even, odd, stick, or no-parity bit generation/detection

　　• 1 or 2 stop bit generation

　　– IrDA serial-IR (SIR) encoder/decoder providing

　　• Programmable use of IrDA Serial Infrared (SIR) or UART input/output

　　• Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex

　　• Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations

　　• Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration

　　■ Synchronous Serial Interface (SSI)

　　– Master or slave operation

　　– Programmable clock bit rate and prescale

　　– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep

　　– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces

　　– Programmable data frame size from 4 to 16 bits

　　– Internal loopback test mode for diagnostic/debug testing

　　■ I2C

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　　Architectural Overview

　　– Devices on the I2C bus can be designated as either a master or a slave

　　• Supports both sending and receiving data as either a master or a slave

　　• Supports simultaneous master and slave operation

　　– Four I2C modes

　　• Master transmit

　　• Master receive

　　• Slave transmit

　　• Slave receive

　　– Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)

　　– Master and slave interrupt generation

　　• Master generates interrupts when a transmit or receive operation completes (or aborts due to an error)

　　• Slave generates interrupts when data has been sent or requested by a master

　　– Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode

　　■ Controller Area Network (CAN)

　　– CAN protocol version 2.0 part A/B

　　– Bit rates up to 1 Mbps

　　– 32 message objects with individual identifier masks

　　– Maskable interrupt

　　– Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN) applications

　　– Programmable Loopback mode for self-test operation

　　– Programmable FIFO mode enables storage of multiple message objects

　　– Gluelessly attaches to an external CAN interface through the CANnTX and CANnRX signals

　　■ 10/100 Ethernet Controller

　　– Conforms to the IEEE 802.3-2002 specification

　　• 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer interface to the line

　　• 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler

　　• Full-featured auto-negotiation

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　　– Multiple operational modes

　　• Full- and half-duplex 100 Mbps

　　• Full- and half-duplex 10 Mbps

　　• Power-saving and power-down modes

　　– Highly configurable

　　• Programmable MAC address

　　• LED activity selection

　　• Promiscuous mode support

　　• CRC error-rejection control

　　• User-configurable interrupts

　　– Physical media manipulation

　　• Automatic MDI/MDI-X cross-over correction

　　• Register-programmable transmit amplitude

　　• Automatic polarity correction and 10BASE-T signal reception

　　– IEEE 1588 Precision Time Protocol - provides highly accurate time stamps for individual packets

　　■ Analog Comparators

　　– One integrated analog comparator

　　– Configurable for output to drive an output pin, generate an interrupt, or initiate an ADC sample sequence

　　– Compare external pin input to external pin input or to internal programmable voltage reference

　　– Compare a test voltage against any one of these voltages

　　• An individual external reference voltage

　　• A shared single external reference voltage

　　• A shared internal reference voltage

　　■ PWM

　　– Three PWM generator blocks, each with one 16-bit counter, two PWM comparators, a PWM

　　signal generator, a dead-band generator, and an interrupt/ADC-trigger selector

　　– One fault input in hardware to promote low-latency shutdown

　　– One 16-bit counter

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　　Architectural Overview

　　• Runs in Down or Up/Down mode

　　• Output frequency controlled by a 16-bit load value

　　• Load value updates can be synchronized

　　• Produces output signals at zero and load value

　　– Two PWM comparators

　　• Comparator value updates can be synchronized

　　• Produces output signals on match

　　– PWM generator

　　• Output PWM signal is constructed based on actions taken as a result of the counter and PWM comparator output signals

　　• Produces two independent PWM signals

　　– Dead-band generator

　　• Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge

　　• Can be bypassed, leaving input PWM signals unmodified

　　– Flexible output control block with PWM output enable of each PWM signal

　　• PWM output enable of each PWM signal

　　• Optional output inversion of each PWM signal (polarity control)

　　• Optional fault handling for each PWM signal

　　• Synchronization of timers in the PWM generator blocks

　　• Interrupt status summary of the PWM generator blocks

　　– Can initiate an ADC sample sequence

　　■ QEI

　　– Two QEI modules, each with the following features:

　　– Position integrator that tracks the encoder position

　　– Velocity capture using built-in timer

　　– The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 12.5 MHz for a 50-MHz system)

　　– Interrupt generation on:

　　• Index pulse

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　　• Velocity-timer expiration

　　• Direction change

　　• Quadrature error detection

　　■ Power

　　– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V

　　– Hibernation module handles the power-up/down 3.3 V sequencing and control for the core digital logic and analog circuits

　　– Low-power options on controller: Sleep and Deep-sleep modes

　　– Low-power options for peripherals: software controls shutdown of individual peripherals

　　– 3.3-V supply brown-out detection and reporting via interrupt or reset

　　■ Flexible Reset Sources

　　– Power-on reset (POR)

　　– Reset pin assertion

　　– Brown-out (BOR) detector alerts to system power drops

　　– Software reset

　　– Watchdog timer reset

　　– Internal low drop-out (LDO) regulator output goes unregulated

　　■ Industrial and extended temperature 100-pin RoHS-compliant LQFP package

　　■ Industrial-range 108-ball RoHS-compliant BGA package 1.2 Target Applications

　　■ Remote monitoring

　　■ Electronic point-of-sale (POS) machines

　　■ Test and measurement equipment

　　■ Network appliances and switches

　　■ Factory automation

　　■ HVAC and building control

　　■ Gaming equipment

　　■ Motion control

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　　Architectural Overview

　　■ Medical instrumentation

　　■ Fire and security

　　■ Power and energy

　　■ Transportation

　　The LM3S8962 应用特点：

　　The Stellaris LM3S8962 Evaluation Kit includes the following features:

　　Stellaris LM3S8962 microcontroller with fully-integrated 10/100 embedded Ethernet controller and CAN module

　　Simple setup; USB cable provides serial communication, debugging, and power

　　OLED graphics display with 128 x 96 pixel resolution

　　User LED, navigation switches, and select pushbuttons

　　Magnetic speaker

　　MicroSD card slot

　　USB interface for debugging and power supply

　　Standard ARM® 20-pin JTAG debug connector with input and output modes

　　LM3S8962 I/O available on labeled break-out pads

　　Standalone CAN device board using Stellaris LM3S2110 microcontroller