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基于TI公司的DAC3XJ8X很低功耗电16位四路2.5 GSPS DAC解决方案

来源: 中电网
2019-04-16
类别:电源管理
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文章创建人 拍明

原标题:TI DAC3XJ8X很低功耗电16位四路2.5 GSPS DAC解决方案

  TI公司的DAC37J84/dac38j84系列是非常低功耗16位四路1.6/2.5 GSPS DAC,其JESD204B接口高达12.5Gbps,最大输入数据速率1.23GSPS, 在2.5GSPS时的功耗为1.8W,主要用在基站,发送器,宽带通信,直接数字合成(DDS)仪表,毫米波/微波骨干网,自动测试设备(ATE)和有线通信等.本文介绍了DAC37J84/DAC38J84主要特性和框图, 评估模块DAC3XJ8XEVM主要特性和简化框图,电路图,材料清单和PCB元件布局图.

  The pin-compatible DAC37J84/DAC38J84 family is a very low power, 16-bit, quad-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface up to 12.5 Gbps. The maximum input data rate is 1.23 GSPS. The DAC37J84/DAC38J84 family is also pin-compatible with the 16-bit, dual-channel, 1.6/2.5GSPS DAC37J82/DAC38J82 family.

  Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.

  The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement. A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.

  The DAC37J84/DAC38J84 family is packaged in a 10×10mm 144-pin flip-chip BGA. The DAC37J84/ DAC38J84 family is specified over the full industrial temperature range (−40℃ to 85℃).

  DAC37J84/DAC38J84主要特性:

  Resolution: 16-Bit

  Maximum Sample Rate:

  DAC37J84: 1.6 GSPS

  DAC38J84: 2.5 GSPS

  Maximum Input Data Rate: 1.23GSPS

  JESD204B Interface

  8 JESD204B Serial Input Lanes

  12.5 Gbps Maximum Bit Rate per Lane

  Subclass 1 Multi-DAC Synchronization

  On-Chip Very Low Jitter PLL

  Selectable 1x -16x Interpolation

  Independent Complex Mixers with 48-bit NCO/ or ±n×Fs/8

  Wideband Digital Quadrature Modulator Correction

  Sinx/x Correction Filters

  Fractional Sample Group Delay Correction

  Multi-Band Mode: Digital Summation of Independent Complex Signals

  3/4-Wire Serial Control Bus (SPI):1.5V – 1.8V

  Integrated Temperature Sensor

  JTAG Boundary Scan

  Pin-compatible with Dual-channel DAC37J82/ DAC38J82 family

  Power Dissipation: 1.8W at 2.5GSPS

  Package: 10×10mm, 144-Ball Flip-Chip BGA

  DAC37J84/DAC38J84应用:

  • Cellular Base Stations.

  • Diversity Transmit

  • Wideband Communications

  • Direct Digital Synthesis (DDS) instruments

  • Millimeter/Microwave Backhaul

  • Automated Test Equipment

  • Cable Infrastructure

  图1. DAC37J84/DAC38J84方框图

  评估模块DAC3XJ8XEVM

  The DAC3XJ8XEVM is an evaluation module (EVM) designed to evaluate the DAC3XJ8X family of high-speed, JESD204B interface DACs (DAC37J82, DAC37J84, DAC38J82, DAC38J84). The EVM includes an onboard clocking solution (LMK04828), transformer coupled outputs, full power solution, and easy-to-use software GUI and USB interface.

  The DAC3XJ8XEVM is designed to work seamlessly with the TSW14J56EVM, Texas Instruments’ JESD204B pattern generator card, through the High Speed Data Converter Pro (HSDCPro) software tool for high-speed data converter evaluation. The DAC3XJ8XEVM was also designed to work with many of the development kits from leading FPGA vendors that contain an FMC connector.

  The DAC3XJ8XEVM is intended for evaluation of the DAC3XJ8X family of high-speed, JESD204B

  interface DACs. The digital input signal to the DAC is provided from the FMC connector (J16) on up to eight 12.5-Gbps SerDes lanes using the JESD204B interface standard. The FMC connector is also used for the SYNC signal required to establish the JESD204B link and both device clock and SYSREF signal for the FPGA.

  The analog output of the DAC3XJ8X can be monitored on the installed SMA connectors labeled IOUTA through IOUTD for channels A through D, respectively. The analog outputs are transformer coupled and do not pass low frequency signals below approximately 10 MHz. The transformer converts the differential DAC output to a single-ended output for use with common laboratory equipment.

  The clocks for the DAC and FPGA are distributed using the LMK04828 ultra low-noise clock jitter cleaner for JESD204B applications. The LMK04828 can be setup in a variety of configurations including clock distribution mode and dual-loop jitter cleaning mode. In clock distribution mode, the desired DAC output rate is provided to the CLKIN connector and the LMK04828 divides and distributes the device clocks and SYSREF signals. In dual-loop mode, the CLKIN connector can be used to provide a reference to the LMK04828, but the clocks are generated on board using the LMK04828 PLL and onboard 122.88 MHz VCXO.

  评估模块DAC3XJ8XEVM主要特性:

  Allows comprehensive testing of the DAC3XJ8X family of high-speed, JESD204B interface DACs

  Transformer-coupled signal path enables direct performance testing of the DAC3XJ8X outputs

  Simplified testing using the onboard LMK04828 JESD204B clocking solution for clock generation, jitter cleaning, or distribution Easy and intuitive software GUI reduces setup time and provides full access to device features Designed for use with TI’s TSW14J56 JESD204B pattern capture and generation tool

  FMC connector enables use of the DAC3XJ8XEVM with many of the leading FPGA vendor’s development kits

  图2. 评估模块DAC37J84EVM外形图

  图3.评估模块DAC3XJ8XEVM简化框图

  图4.评估模块DAC3XJ8XEVM电路图(1)




责任编辑:HanFeng

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