原标题：DSP下的车载导航系统硬件电路设计

数字信号微处理器DSP具有高速运行与数据处理的功能,以其高性能和低功耗的优势为实时导航系统的数学计算提供了有效的硬件平台。在现代武器装备中,设计了基于DSP芯片的车载导航系统,其在民用和军事领域均发挥着重要作用,系统具有高可靠性、安全性等特点。

1 车载导航系统工作原理

车载导航系统的主要功能是定时采集陀螺正交编码信号、加速度计的输入和里程计输入信号,并对采集的数据进行必要的处理,以实现导航解算。同时将采集数据通过RS422总线和CAN总线发送至地面监测设备;并通过RS422总线接收相关的命令及参数。该系统结构如图1所示。

图1 车载导航系统结构框图

2 系统硬件设计

2.1 处理器及存储器设计

车载导航系统电路采用TI公司的TMS320C6713B-A200作为DSP,该DSP芯片标称主频为200 MHz,工作在160 MHz主频时DSP处理能力为1600 MI·s-1/1 200MFLOPS。使用40 MHz的晶振作为DSP的时钟输入,经内部锁相环倍频后作为DSP工作的时钟,使用一片TPS70345电压调整器为其提供3.3 V的IO电压和1.2 V的内核电压;采用一片容量为16 MB的MT48LC4M3282TG-7IT芯片作为SDRAM的存储器,存储器直接接入DSP的EMIF总线上,SDRAM芯片的地址线BA1、BA0和A11～A0接DSP芯片的EA15～EA2,数据线D31～D0接ED31～ED0。FlashRom芯片的地址线A22～A0接DSP芯片的GP13～CP11和EA21～EA2,数据线DQ15～DQ0,接ED15～ED0,初始化时GP13～GP13个引脚的状态为高,SDRAM芯片的片选信号接DSP芯片的CE0;采用一片容量为16 MB的S29GL128N10TFIR1芯片为FlashRom存储器,FlashRom芯片的片选信号接DSP芯片的CE1。之所以DSP芯片的CE1接到FlashRom的片选上,是因其引导方式采用从ROM加载,BOOT程序存放在FlashRom存储器中。存储器的读写信号均接到DSP芯片的AWE信号上。DSP通过EMIF总线接口访问外部存储器,可通过操作寄存器控制对外部存储器的访问,简化了电路的设计。

2.2 电源设计

车载导航系统输入电源为27±9 V,经MHF+28515将24 V转换为+15 V和+5 V的电压,MHF+28515的输入电压范围为16～48 V,输出功率15 W,其中+5 V电压输出最大功率为7.5 W,电流1 500 mA,+15 V电压输出功率最大分别为5 W,电路330 mA。由于车载导航系统电路自身+5 V电源使用的电流约为1000 mA,所以能提供+5 V,电流》140 mA的输出给外部使用,为满足系统中各部件的供电要求,设计了车载导航系统供电系统。

MHF+28515输出的+5 V电源为整个模块提供数字电源,其中CAN总线协议芯片等部分+5 V工作的芯片直接使用该电源;其他电路使用经转换后的电源其处理方法包括:通过电压调整器TPS70345将+5 V电源转换成3.3 V和1.2 V电源,其中3.3 V供DSP外围电路及SDRAM、Flash等芯片使用,1.2 V供DSP内核使用;通过电压调整器TPS70351将+5 V电源转换成3.3 V和1.8 V电压,其中3.3 V供FPGA外围电路、光耦等芯片使用,1.8 V供FPGA内核使用;通过两个DC/DC模块NKE0503将+5 V电源转换成3.3 V电压,一个供RS422隔离电路中的MAX3490及光耦使用,另一个供RS232隔离电路中的MAX3232及光耦使用。通过一个DC/DC模块NME0505将+5 V电源进行隔离,供MAX481、CAN总线收发器和其通路上的光耦使用。MHF+28515输出的±15 V电源为整个模块提供模拟电源,其中+15 V电压通过三端稳压器JW78M05将电压转换成+5 V模拟电压,供LM3940IMP和REF196使用;+5 V模拟电压通过LM3940IMP转换成3.3 V模拟电压,为运放供电;+5 V模拟电压通过REF196转换成3.3 V模拟电压,为电桥供电;+15 V和-15 V电压则是为运放OP497供电。

2.3 输入信号

车载导航系统电路输入信号有3路加速度计信号、3路陀螺信号、两路里程计信号、两路标频信号、一路行车状态信号、9路状态检测信号和10路测温信号。

加速度计信号的信号形式为可逆脉冲,幅值TTL,满量程为256 kHz,经3路16位计数器计数,上升沿触发,中断5锁存,加速度计信号采用RC滤波和带施密特触发输入的反向器进行整形处理,然后通过74LVC244进行电平转换后引入FPGA中。

陀螺信号的信号形式为正交编码信号,幅值高电平4～5 V,低电平0～0.8 V,电流≤8 mA,频率≤1.5 MHz,相位差90°±20°,经3路16位计数器计数,上升沿触发,中断5锁存,陀螺信号也与加速度计信号相同,进行整形处理。而标频信号频率为128 kHz,幅值TTL,也信号需整形。因此,标频信号的处理形式和加速度计信号处理方法相同。

里程计信号包括两路里程计信号、1路行车状态信号和1路里程计地,幅值12 V,驱动能力30 mA,需光耦隔离,设置两个16位计数器和1位状态寄存器,分别记录里程计脉冲输入和状态信息,里程计脉冲上升沿触发计数,中断5锁存;要求行车状态信号State可用命令使能和禁止,使能状态下当State=1时,里程计信号加法计数;当State=0时,减法计数;禁止状态下里程计信号加法计数,里程计信号先经RC滤波电路和保护二极管,然后经光隔进入FPGA。

状态检测信号包括3路跳模检测信号、3路高压状态信号和3路机抖状态信号,信号形式均为开关量,幅值为TTL,机抖状态信号和高压状态信号需光耦隔离。跳模检测信号处理形式和参数选择与加速度计信号相同;高压状态信号和机抖检测信号处理形式则与陀螺信号一致。

测温信号包括10路测温电阻输入和1路测温电阻输入公共端,温度范围在-45～+70℃,测温电阻与模块上3个高精度电阻组成电桥,按照电桥工作原理,桥臂电阻的阻值应小于测温电阻的最小值,并应当考虑一定的冗余,温度系数的计算公式为R0×3.85×10-3,其中R0是0℃电阻,由于采用了高精度电阻和12位的AD,A/D转换精度》0.5 ℃,可用多路开关实现。电桥两臂中点分别接入运算放大器进行跟随处理,再经后级放大后由A/D转换芯片采集温度测试结果,A/D转换芯片采用串行接口芯片,与DSP的McBSP1接口连接,该芯片分辨率为12位,并具有10 μs的转换时间及最大11路的A/D输入。

在车载导航系统电路设计中采用了CAN总线设计。CAN总线独立控制器采用SJA1000T,使用16 MHz晶振作为时钟输入,可通过软件配置ID号和数据传输波特率,最大速率为1 Mbit·s-1。其总线控制器使用数据地址复用总线,经FPGA转换后与DSPEMIF总线连接。CAN总线控制器信号采用TTL电平(5 V),与信号为3.3 V电平的FPGA之间需使用SN74LVC4245作电平转换。CAN总线接收器采用Philips Semiconductors公司PCA82C250。其总线控制器与收发器之间的数据传输信号采用光耦进行隔离。CAN总线接口电路如图2所示。

图2 CAN总线接口电路

2.4 FPGA设计

车载导航系统电路采用FPGA处理模块上控制逻辑、各输入信号的计数及实现串行接口通讯协议。FPGA对输入信号进行计数,并对标频信号分频产生中断5信号,产生中断5信号的同时对各计数器值进行锁存。DSP可通过EMIF总线访问FPGA的内部资源,地址空间占用EMIF总线的CE2。FPGA的加载模式为主控串行模式(Master Serial Mode),FPGA功能框图如图3所示。FPGA设计包括加速度计信号计数器设计、陀螺信号计数器设计、里程计信号计数器设计、陀螺合频计数器设计、标频分频器设计、状态检测、故障检测信号和串行通讯接口设计。

图3 FPGA功能框图

加速度计信号输入为可逆脉冲,每个通道加速度计输入包括3路信号,分别是+A、-A和GND,按照设计要求,+A信号上有脉冲时计数值增加,-A信号上有脉冲时计数值减少,当频标分频中断产生时,将计数结果存入锁存器内。在FPGA中设计了16位的计数器,上电复位计数器为0,+A信号上有脉冲时计数值加1,-A信号上有脉冲时计数值减1,当频标分频中断产生时,将计数结果存入锁存器内,DSP可通过EMIF访问锁存器得到加速度计信号计数器的结果。

陀螺信号输入形式为正交编码信号,每个通道陀螺信号输入包括3路信号,分别是A、B和DGND,当A相超前B相90°时计数值增加,当A相落后B相90°时计数值减少。在设计时输入信号先经过鉴相电路,识别A路和B路信号的相位先后,并产生两路4倍频的可逆脉冲信号,然后对可逆脉冲进行计数,当标频信号中断产生时,将计数结果存入锁存器内。

里程计信号包括两路计数输入和一路行车状态信号输入,计数输入每路使用一个16 bit计数器,当中断产生时将计数器数值存入锁存器;行车状态信号(STATE)上电初始为无效状态,用户通过命令设置STATE状态是否有效。其STATE信号处于有效状态时,STATE为1,里程计计数器递增计数;若STATE为0时,里程计计数器递减计数;而当STATE信号处于无效状态时,里程计计数器递增计数。

在FPGA中设计了16位计数器,上电复位计数器为0,计数器的值均增加,而计数器均加1,当频标分频中断产生时,将计数结果存入锁存器内。DSP可通过EMIF访问锁存器得到陀螺合频计数器的结果。

标频分频器用来将标频信号分频,产生锁存FPGA内加速度计数器、陀螺计数器、里程计计数器的计数值以及状态检测信号的状态中断信号。在FPGA中标频分频器由一个预定标器和一个计数器组成,可由软件编程设置分频,DSP通过EMIF总线向预定标器写入需分频的数值,计数器记录频标脉冲的个数,计数至定标值时计数器输出并清零,而计数器输出至DSP的中断,同时锁存FPGA内加速度计数器、陀螺计数器、里程计计数器的计数值以及状态检测信号的状态。

状态检测信号为开关量信号,状态存放在一个地址中,每一位代表一路的状态。在FPGA中设计一个16位的寄存器,存放行车状态、高压检测信号状态、机抖检测信号状态及跳模检测信号状态,并在中断时将信号锁存到锁存器中。

故障检测信号是通过一个地址写入故障检测向量,根据故障检测向量每一位具体是0或1,由可编程逻辑器件将故障检测向量自动设置输出引脚。在FPGA中设置一个8位的存储器,用于存放故障检测向量,信号经驱动后输出。

FPGA内部设计了串行协议模块,经外接电路组成RS232和RS422串行接口。集成协议芯片参照ST16C2552进行设计,对其MODEM控制等功能进行了裁减。而串行接口工作波特率也均可设置。

【TMS320C6713B】

浮点数字信号处理器

描述

The TMS320C67x™ DSPs (including the TMS320C6713B device) compose the floating-point DSP generation in the TMS320C6000™ DSP platform. The C6713B device is based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications.

Operating at 225 MHz, the C6713B delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS).

Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second (MFLOPS), 2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million multiply-accumulate operations per second (MMACS).

The C6713B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-byte memory space that is shared between program and data space. 64K bytes of the 256K bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K bytes in L2 serves as mapped SRAM.

The C6713B has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals.

The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713B has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The two I2C ports on the TMS320C6713B allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The TMS320C6713B device has two bootmodes: from the HPI or from external asynchronous ROM. For more detailed information, see the bootmode section of this data sheet.

The TMS320C67x DSP generation is supported by the TI eXpressDSP™ set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio™ Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS™ kernel.

特性

Highest-Performance Floating-Point Digital Signal Processor (DSP): TMS320C6713B

Eight 32-Bit Instructions/Cycle

32/64-Bit Data Word

300-, 225-, 200-MHz (GDP and ZDP), and 225-, 200-, 167-MHz (PYP) Clock Rates

3.3-, 4.4-, 5-, 6-Instruction Cycle Times

2400/1800, 1800/1350, 1600/1200, and 1336/1000 MIPS/MFLOPS

Rich Peripheral Set, Optimized for Audio

Highly Optimized C/C++ Compiler

Extended Temperature Devices Available

Advanced Very Long Instruction Word (VLIW) TMS320C67x™ DSP Core

Eight Independent Functional Units:

2 ALUs (Fixed-Point)

4 ALUs (Floating-/Fixed-Point)

2 Multipliers (Floating-/Fixed-Point)

Load-Store Architecture With 32 32-Bit General-Purpose Registers

Instruction Packing Reduces Code Size

All Instructions Conditional

Instruction Set Features

Native Instructions for IEEE 754

Single- and Double-Precision

Byte-Addressable (8-, 16-, 32-Bit Data)

8-Bit Overflow Protection

Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization

L1/L2 Memory Architecture

4K-Byte L1P Program Cache (Direct-Mapped)

4K-Byte L1D Data Cache (2-Way)

256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and 192K-Byte Additional L2 Mapped RAM

Device Configuration

Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot

Endianness: Little Endian, Big Endian

32-Bit External Memory Interface (EMIF)

Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM

512M-Byte Total Addressable External Memory Space

Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)

16-Bit Host-Port Interface (HPI)

Two McASPs

Two Independent Clock Zones Each (1 TX and 1 RX)

Eight Serial Data Pins Per Port: Individually Assignable to any of the Clock Zones

Each Clock Zone Includes:

Programmable Clock Generator

Programmable Frame Sync Generator

TDM Streams From 2-32 Time Slots

Support for Slot Size:

8, 12, 16, 20, 24, 28, 32 Bits

Data Formatter for Bit Manipulation

Wide Variety of I2S and Similar Bit Stream Formats

Integrated Digital Audio Interface Transmitter (DIT) Supports:

S/PDIF, IEC60958-1, AES-3, CP-430 Formats

Up to 16 transmit pins

Enhanced Channel Status/User Data

Extensive Error Checking and Recovery

Two Inter-Integrated Circuit Bus (I2C Bus™) Multi-Master and Slave Interfaces

Two Multichannel Buffered Serial Ports:

Serial-Peripheral-Interface (SPI)

High-Speed TDM Interface

AC97 Interface

Two 32-Bit General-Purpose Timers

Dedicated GPIO Module With 16 pins (External Interrupt Capable)

Flexible Phase-Locked-Loop (PLL) Based Clock Generator Module

IEEE-1149.1 (JTAG) Boundary-Scan-Compatible

208-Pin PowerPAD™ PQFP (PYP)

272-BGA Packages (GDP and ZDP)

0.13-µm/6-Level Copper Metal Process

CMOS Technology

3.3-V I/Os, 1.2-V Internal (GDP/ZDP/ PYP)

3.3-V I/Os, 1.4-V Internal (GDP/ZDP) [300 MHz]