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基于S3C2440/XC3S200A/DM355/THS7327的安防系统、影视展厅解决方案

来源: 电子方案网
2018-11-08
类别:LED应用
eye 30
文章创建人 拍明芯城

原标题:安防系统、影视展厅


应用领域:照明显示

方案类型:模块板卡

主要芯片:TI;海思;VISHAY;XMOS;

方案概述

采用三星S3C2440处理器,运行速度更快,系统更稳定

采用FPGA可编程逻辑阵列电路XC3S200A,性能更稳定;

采用美国TI公司DM355数字视频处理芯片,图像特别清晰;

采用美国TI公司THS7327长距离VGA驱动芯片,驱动距离高达80米

采用750M高带宽芯片,具有长线驱动功能;

支持2048X1536高分辨率设计电路

采用信号长距离传输失真增益补偿技术;

采用数字同步识别处理(DSIP)技术

支持无缝集成CMMAW技术和CCSEB电源管理技术;

采用3D全新蓝色矩阵式显示屏,全中文显示工作状态

内置轮循切换功能,能任意设定间隔时间和通道

内置32组场景存储功能,能直接在面板操作

32路RGB电脑信号输入;8/16/32路RGB电脑信号输出;

RGB视频输入和输出端采用5个BNC母接口;

专用端口,能直接和富泰尔无线触摸屏连接,即插即用;

全贴片SMD工艺,特有ESD静电保护功能;

RGB视频切换器是专门为RGB视频信号的显示切换而设计的高性能智能矩阵开关设备,用于将各路RGB视频输出通道中的任一通道上,该系列产品广泛用于大屏幕投影显示工程、电化教学、指挥控制中心、多媒体会议室等场合;

本产品是具有高可靠性的智能设备,设计中采用容错技术,并采用了高抗干扰能力的通信接口电路,保证了通信的可靠性,具有红外遥控功能和RS232通信功能,用户可以方便的完成演示过程中的信号切换;

本产品带有断电现现场切换记忆保护、视频同步或分离切换等功能,具备RS232通讯通讯接口,可以方便与电脑、遥控系统或各种远端控制设备配合使用;

全球通用宽电压设计,可适应交流100~240V,50/60Hz;

高品质、大批量生产,有较高的兼容性和稳定性,有较高的性价比;

基于S3C2440/XC3S200A/DM355/THS7327的安防系统、影视展厅解决方案.jpg

【S3C2440】

S3C2440A被设计为手持设备和为一般应用提供低功耗,高性能的微控制器解决方案的小尺寸芯片。为了降低系统总成本,S3C2440A包括以下组件。

S3C2440A以 ARM920T为核心,采用0.13um CMOS标准单元和存储器编译器开发。它的低功耗,简单,优雅和全静态设计特别适合于成本和功耗敏感的应用。它采用了被称为高级微控制器总线架构(AMBA)的新的总线架构。

S3C2440A提供了出色的功能,其CPU内核,一个32位ARM920T RISC处理器设计的高级RISC机, ARM920T实现了MMU,AMBA总线,和哈佛缓存架构与独立的16KB指令和16KB数据高速缓存,每一个字线的长度为8。

S3C2440A减少了系统整体成本,无需配置额外的组件通过提供一套完整的通用系统外设。

特征

手持设备和通用嵌入式应用的集成系统

16/32-位RISC架构和以ARM920T CPU为核心的强大的指令集

增强ARM架构的MMU支持WinCE,EPOC32和Linux

指令缓存,数据缓存,写缓冲和物理地址TAG RAM性能,以减少主内存带宽和延迟的效果

系统功能

小/大尾数法支持

支持快速总线模式和异步总线模式

每个堆栈总1G字节)的地址空间:128M字节。

每个堆栈支持可编程8/16/32位数据总线宽度

堆栈固定起始地址0至6

可编程堆栈的起始地址和堆栈规模是7


【XC3S200A】

介绍斯巴达™ -3系列现场可编程门阵列是专门设计来满足高容量的需求,成本敏感的消费电子应用。该八口之家提供的密度范围从5万到500万个系统门,如图表1中。在Spartan-3系列是建立在早先的成功的Spartan- IIE系列通过增加逻辑量资源,内部RAM的容量,总数的I / O ,以及性能的总体水平,以及通过提高时钟管理功能。众多从增强国家的最先进的的Virtex得到™-II技术。这些Spartan-3系列的增强,结合先进的工艺技术,实现了更多的功能和每美元的带宽比以前可能,设定在可编程逻辑行业廷的新标准。因为他们的成本非常低, Spartan-3系列FPGA中的非常适用于广泛的消费电子产品应用,包括宽带接入,家庭网络 -荷兰国际集团,显示器/投影和数字电视设备。在Spartan-3系列是一个更好的选择,以掩盖亲编程的ASIC。 FPGA的避免了初期成本高,在漫长的开发周期,以及固有的僵化传统的ASIC。此外, FPGA的可编程许可证设计升级,在现场没有更换硬件必要时,是不可能用的ASIC。•-••••••••

特点

•成本极低,适用于高性能逻辑解决方案大容量,面向消费者的应用- 密度高达74880个逻辑单元三电源轨:核心( 1.2V ) , I / O的( 1.2V至3.3V ) ,和辅助用途( 2.5V )

•的SelectIO ™信号- 多达784个I / O引脚- 每次我622 Mb / s的数据传输率/ O- 18单端信号标准- 6差分I / O标准,包括LVDS , RSDS- 终止了数控阻抗- 信号摆幅范围为1.14V至3.45V- 双数据速率( DDR )支持逻辑资源- 丰富的逻辑单元与移位寄存器功能- 宽多路复用器- 快速先行进位逻辑- 专用18× 18乘法器- 符合IEEE 1149.1 / 1532兼容的JTAG逻辑SelectRAM ™分层存储- 截至1872 Kbits的总块RAM的- 高达520 Kbit的总分布式RAM的数字时钟管理器(最多四个DCM的)- 时钟偏移消除- 频率合成- 高分辨率移相八个全局时钟线和丰富的路由赛灵思ISE开发系统完全支持- 综合,映射,布局和布线的MicroBlaze ™处理器,PCI和其它芯无铅封装选项低功耗Spartan -3L系列和汽车Spartan-3系列XA系列选项

【TMS320DM355】

数字媒体片上系统 (DMSoC)

TMS320DM355.png

描述

The DM355 is a highly integrated, programmable platform for digital still camera, digital photo frames, IP security cameras, 4-channel digital video recorders, video door bell application, and other low cost portable digital video applications. Designed to offer portable video designers and manufacturers the ability to produce affordable portable digital video solutions with high picture quality, the DM355 combines high performance MPEG4 HD (720p) codecs and JPEG codecs up to 50M pixels per second, high quality, and low power consumption at a very low price point. The DM355 also enables seamless interface to most additional external devices required for a complete digital camera implementation. The interface is flexible enough to support various types of CCD and CMOS sensors, signal conditioning circuits, power management, DDR/mDDR memory, SRAM, NAND, shutter, Iris and auto-focus motor controls, etc.

The DM355 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates:

A coprocessor 15 (CP15) and protection module

Data and program Memory Management Units (MMUs) with table look-aside buffers.

Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

DM355 performance is enhanced by its MPEG4/JPEG coprocessor. The MPEG4/JPEG coprocessor performs the computational operations required for image processing; JPEG compression and MPEG4 video and imaging standard. The MPEG4/JPEG coprocessor supports MPEG4 SP at HD (720p), D1, VGA, SIF encode/decode resolutions and JPEG encode/decode up to 50M pixels per second.

The DM355 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:

A Video Processing Front-End (VPFE)

A Video Processing Back-End (VPBE)

The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.

The DM355 peripheral set includes:

An inter-integrated circuit (I2C) Bus interface

Two audio serial ports (ASP)

Three 64-bit general-purpose timers each configurable as two independent 32-bit timers

A 64-bit watchdog timer

Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals

Three UARTs with hardware handshaking support on one UART

Three serial port Interfaces (SPI)

Four pulse width modulator (PWM) peripherals

Four real time out (RTO) outputs

Two Multi-Media Card / Secure Digital (MMC/SD/SDIO) interfaces

Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO

A USB 2.0 full and high-speed device and host interface

Two external memory interfaces:

An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as NAND and OneNAND.

A high speed synchronous memory interface for DDR2/mDDR.

For software development support the DM355 has a complete set of ARM development tools which include: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

特性

Get started today with production-ready, easy-to-use audio and video codecs for digital media processors based on DaVinci™ technology. Also available are various O/S Board Support Packages and software updates. All codecs are available for FREE evaluation. REQUEST FREE SOFTWARE!

High-Performance Digital Media System-on-Chip (DMSoC)

Up to 270-MHz ARM926EJ-S™ Clock Rate

MPEG4/JPEG Coprocessor Supports

Up to 720p MPEG4 SP

Up to 50M Pixels per Second JPEG

Video Processing Subsystem

Hardware IPIPE for Real-Time Image Processing

Up to 14-bit CCD/CMOS Digital Interface

Histogram Module

Resize Image 1/16x to 8x

Hardware On-Screen Display

Supports digital HDTV (720p/1080i) output for connection to external encoder

Peripherals include DDR and mDDR SDRAM, 2 MMC/SD/SDIO and SmartMedia Flash Card Interfaces, USB 2.0, 3 UARTs and 3 SPIs

Configurable Power-Saving Modes

On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART

Extended Temperature 135- and 216-MHz Devices are Available

3.3-V and 1.8-V I/O, 1.3-V Core

Debug Interface Support

337-Pin Ball Grid Array at 65 nm Process Technology

High-Performance Digital Media System-on-Chip

135-, 216-, and 270-MHz ARM926EJ-S Clock Rate

Fully Software-Compatible With ARM9

Extended Temperature support for 135- and 216-Mhz Devices are Available

ARM926EJ-S Core

Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets

DSP Instruction Extensions and Single Cycle MAC

ARM® Jazelle® Technology

EmbeddedICE-RT™ Logic for Real-Time Debug

ARM9 Memory Architecture

16K-Byte Instruction Cache

8K-Byte Data Cache

32K-Byte RAM

8K-Byte ROM

Little Endian

MPEG4/JPEG Coprocessor

Fixed Function Coprocessor Supports:

MPEG4 SP Codec at HD (720p), D1, VGA, SIF

JPEG Codec up to 50M Pixels per Second

Video Processing Subsystem

Front End Provides:

Hardware IPIPE for Real-Time Processing

up to 14-bit CCD/CMOS Digital Interface

16-/8-bit Generic YcBcR-4:2 Interface (BT.601)

10-/8-bit CCIR6565/BT655 Interface

Up to 75-MHz Pixel Clock

Histogram Module

Resize Engine

Resize Images From 1/16x to 8x

Separate Horizontal/Vertical Control

Two Simultaneous Output Paths

Back End Provides:

Hardware On-Screen Display (OSD)

Composite NTSC/PAL video encoder output

8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output

BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface

Supports digital HDTV (720p/1080i) output for connection to external encoder

External Memory Interfaces (EMIFs)

DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)

Asynchronous16-/8-bit Wide EMIF (AEMIF)

Flash Memory Interfaces

NAND (8-/16-bit Wide Data)

OneNAND(16-bit Wide Data)

Flash Card Interfaces

Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)

SmartMedia

Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)

USB Port with Integrated 2.0 High-Speed PHY that Supports

USB 2.0 Full and High-Speed Device

USB 2.0 Low, Full, and High-Speed Host

Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)

One 64-Bit Watch Dog Timer

Three UARTs (One fast UART with RTS and CTS Flow Control)

Three Serial Port Interfaces (SPI) each with two Chip-Selects

One Master/Slave Inter-Integrated Circuit (I2C) Bus®

Two Audio Serial Port (ASP)

I2S and TDM I2S

AC97 Audio Codec Interface

S/PDIF via Software

Standard Voice Codec Interface (AIC12)

SPI Protocol (Master Mode Only)

Four Pulse Width Modulator (PWM) Outputs

Four RTO (Real Time Out) Outputs

Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)

On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART

Configurable Power-Saving Modes

Crystal or External Clock Input (typically 24 MHz or 36 MHz)

Flexible PLL Clock Generators

Debug Interface Support

IEEE-1149.1 (JTAG) Boundary-Scan-Compatible

ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory

Device Revision ID Readable by ARM

337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch

90nm Process Technology

3.3-V and 1.8-V I/O, 1.3-V Internal




责任编辑:David

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