原标题：TI DP83867和AM3359双端口以太网PHY参考设计

　　TI公司的双端口吉比特以太网PHY参考设计TIDA-00204采用全特性的PHY收发器和AM3359 Sitara处理器,满足苛刻的工业环境EMI和EMC需求,输入电压从17V到60V,和IEEE 802.3 10BASE-Te, 100BASE-TX与1000BASE-T标准兼容,本文介绍了PHY收发器dp83867主要特性,框图,应用框图以及双端口吉比特以太网PHY参考设计TIDA-00204主要特性,系统框图,电路图和材料清单.

　　The DP83867 is a robust, low power, fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX and 1000BASE-T Ethernet protocols. Optimized for ESD protection, the DP83867 exceeds 8kV IEC 61000-4-2 (direct contact).

　　The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet LANs. It interfaces directly to twisted pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3 Standard Media Independent Interface (MII), the IEEE 802.3 Gigabit Media Independent Interface (GMII) or Reduced GMII (RGMII). The QFP package supports MII/GMII/RGMII whereas the QFN package supports RGMII.

　　The DP83867 provides precision clock synchronization, including a synchronous Ethernet clock output. It has low latency and provides IEEE 1588 Start of Frame Detection.

　　The DP83867 consumes only 490mW (PAP) and 457mW (RGZ) under full operating power. Wake on LAN can be used to lower system power consumption.

　　DP83867主要特性:

　　Ultra Low RGMII Latency TX < 90ns, RX < 290ns

　　Low Power consumption 457mW

　　Exceeds 8kV IEC 61000-4-2 ESD Protection

　　Meets EN55011 Class B Emission Standards

　　16 Programmable RGMII Delay Modes on RX/TX

　　Integrated MDI Termination Resistors

　　Programmable MII/GMII/RGMII Termination Impedance

　　WoL (Wake on LAN) Packet Detection

　　25-MHz or 125-MHz Synchronized Clock Output

　　IEEE 1588 Time Stamp Support

　　RJ45 Mirror Mode

　　Fully Compatible to IEEE 802.3 10BASE-Te, 100BASE-TX, and 1000BASE-T Specification

　　Cable Diagnostics

　　MII, GMII and RGMII MAC Interface Options

　　Configurable I/O Voltage (3.3V, 2.5V, 1.8V)

　　Fast Link up / Link Drop Modes

　　JTAG Support

　　DP83867应用:

　　Motor and Motion Control

　　Industrial FactoryAutomation

　　Industrial Embedded Computing

　　Wired and Wireless Communications

　　Infrastructure

　　Test and Measurement

　　Consumer Electronics

　　图1.DP83867IRPAP功能框图

　　图2.DP83867应用框图

　　双端口吉比特以太网PHY参考设计TIDA-00204

　　EMI/EMC Compliant Industrial Temp Dual Port Gigabit Ethernet PHY Reference Design This design allows for performance evaluation of two industrial grade DP83867IR Gigabit Ethernet PHYs and Sitara™ host processors with integrated Ethernet MAC and Switch. It was developed to meet industrial requirements for EMI and EMC. The application firmware implements a driver for the PHY, UDP and TCP/IP stack and HTTP web server examples. The host processor is configured to boot the pre-installed firmware from on-board SD-Card. A USB virtual COM port offers optional access to the PHYs registers. A JTAG interface allows for own firmware development.

　　以太网PHY参考设计TIDA-00204主要特性:

　　EMI- and EMC-compliant design with wide input voltage range (17-60V) using two DP83867IR Gigabit Ethernet PHYs and AM3359 Sitara™ Processor to work in harsh industrial environments

　　Exceeds CISPR 11 / EN55011 Class A radiated emission requirement by >4.6dB

　　Exceeds IEC61800-3 EMC immunity requirements:

　　+/-6kV ESD CD per IEC 61000-4-2

　　+/-4kV EFT per IEC 61000-4-4

　　+/-2kV Surge per IEC 61000-4-5

　　Sitara™ AM3359 firmware, including UDP and TCP/IP stack and HTTP web server examples, boots from on-board SD-Card allowing easy standalone operation　Access to DP83867IR registers via USB virtual COM port allows for custom specific PHY configurations, like RGMII Delay Mode

　　Hardware support for Start-of-Frame Detect allows implement IEEE1588 PTP

　　图3.以太网PHY参考设计TIDA-00204外形图

　　图4.以太网PHY参考设计TIDA-00204系统框图

　　以太网PHY参考设计TIDA-00204材料清单: