0 卖盘信息
您现在的位置: 首页 > 商城快讯 > 热门方案> 无线互联 > TI AMIC110 32位Sitara ARM MCU开发方案

TI AMIC110 32位Sitara ARM MCU开发方案

2017-10-19
类别:无线互联
eye 2886
文章创建人 拍明芯城
  TI公司的AMIC110是多协议可编程工业通信处理器,为大多数工业以太网和现场总线通信提供随时可用的解决方案.器件基于ARM Cortex-A8处理器,具有可选择外设和工业接口,支持高级操作系统(HLOS),Linux®和TI-RTOS以及其它RTOS.器件CPU工作频率300MHz,具有NEON™ SIMD协处理器,集成了32KB L1指令和32KB数据缓存,256KB L2高速缓存,176KB引导ROM,64KB专用RAM,主要用在工业通信,连接工业设备和底板I/O.本文介绍了AMIC110主要特性,功能框图,以及工业通信引擎AMIC110 ICE主要特性,框图,电路图,材料清单和PCB元件布局图.

  The AMIC110 device is a multiprotocol programmable industrial communications processor providingready-to-use solutions for most industrial Ethernet and fieldbus communications slaves, as well as somemasters. The device is based on the ARM Cortex-A8 processor, peripherals, and industrial interfaceoptions. The device supports high-level operating systems (HLOS). Linux® and TI-RTOS are available freeof charge from TI. Other RTOS are also offered by TI ecosystem partners. The AMIC110 microprocessoris an ideal companion communications chip to the C2000 family of microcontrollers for connected drives.

  The AMIC110 microprocessor contains the subsystems shown in Figure 1 and a brief description ofeach follows:The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor. The PRU-ICSS isseparate from the ARM core, allowing independent operation and clocking for greater efficiency andflexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such asEtherCAT, PROFINET IRT, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos III, and others.

  Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and allsystem-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specializeddata handling operations, custom peripheral interfaces, and in offloading tasks from the other processorcores of SoC.

  AMIC110主要特性:

  • Up to 300-MHz Sitara™ ARM® Cortex®-A8 32‑BitRISC Processor

  – NEON™ SIMD Coprocessor

  – 32KB of L1 Instruction and 32KB of Data CacheWith Single-Error Detection (Parity)

  – 256KB of L2 Cache With Error Correcting Code(ECC)

  – 176KB of On-Chip Boot ROM

  – 64KB of Dedicated RAM

  – Emulation and Debug - JTAG

  – Interrupt Controller (up to 128 InterruptRequests)

  • On-Chip Memory (Shared L3 RAM)

  – 64KB of General-Purpose On-Chip MemoryController (OCMC) RAM

  – Accessible to All Masters

  – Supports Retention for Fast Wakeup

  • External Memory Interfaces (EMIF)

  – mDDR(LPDDR), DDR2, DDR3, DDR3LController:

  – mDDR: 200-MHz Clock (400-MHz Data Rate)

  – DDR2: 266-MHz Clock (532-MHz Data Rate)

  – DDR3: 400-MHz Clock (800-MHz Data Rate)

  – DDR3L: 400-MHz Clock (800-MHz DataRate)

  – 16-Bit Data Bus

  – 1GB of Total Addressable Space

  – Supports One x16 or Two x8 Memory DeviceConfigurations

  – General-Purpose Memory Controller (GPMC)

  – Flexible 8-Bit and 16-Bit AsynchronousMemory Interface With up to Seven Chip

  Selects (NAND, NOR, Muxed-NOR, SRAM)

  – Uses BCH Code to Support 4-, 8-, or 16-BitECC

  – Uses Hamming Code to Support 1-Bit ECC

  – Error Locator Module (ELM)

  – Used in Conjunction With the GPMC toLocate Addresses of Data Errors from

  Syndrome Polynomials Generated Using aBCH Algorithm

  – Supports 4-, 8-, and 16-Bit per 512-ByteBlock Error Location Based on BCH

  Algorithms

  • Programmable Real-Time Unit Subsystem andIndustrial Communication Subsystem (PRU-ICSS)

  – Supports Protocols such as EtherCAT®,PROFIBUS, PROFINET, EtherNet/IP™, and

  More

  – Two Programmable Real-Time Units (PRUs)

  – 32-Bit Load/Store RISC Processor Capableof Running at 200 MHz

  – 8KB of Instruction RAM With Single-ErrorDetection (Parity)

  – 8KB of Data RAM With Single-Error Detection(Parity)

  – Single-Cycle 32-Bit Multiplier With 64-BitAccumulator

  – Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External

  Signal

  – 12KB of Shared RAM With Single-ErrorDetection (Parity)

  – Three 120-Byte Register Banks Accessible byEach PRU

  – Interrupt Controller (INTC) for Handling SystemInput Events

  – Local Interconnect Bus for Connecting Internaland External Masters to the Resources Insidethe PRU-ICSS

  – Peripherals Inside the PRU-ICSS:

  – One UART Port With Flow Control Pins,Supports up to 12 Mbps

  – One Enhanced Capture (eCAP) Module

  – Two MII Ethernet Ports that Support IndustrialEthernet, such as EtherCAT

  – One MDIO Port

  • Power, Reset, and Clock Management (PRCM)Module

  – Controls the Entry and Exit of Stand-By andDeep-Sleep Modes

  – Responsible for Sleep Sequencing, PowerDomain Switch-Off Sequencing, Wake-Up

  Sequencing, and Power Domain Switch-OnSequencing

  – Clocks

  – Integrated 15- to 35-MHz High-FrequencyOscillator Used to Generate a Reference

  Clock for Various System and PeripheralClocks

  – Supports Individual Clock Enable and DisableControl for Subsystems and Peripherals toFacilitate Reduced Power Consumption

  – Five ADPLLs to Generate System Clocks(MPU Subsystem, DDR Interface, USB and

  Peripherals [MMC and SD, UART, SPI, I2C],L3, L4, Ethernet, GFX [SGX530], LCD Pixel

  Clock (1))

  – Power

  – Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic[WAKEUP])

  – Three Switchable Power Domains (MPUSubsystem [MPU], SGX530 [GFX](1),

  Peripherals and Infrastructure [PER])

  – Implements SmartReflex™ Class 2B for CoreVoltage Scaling Based On Die Temperature,Process Variation, and Performance(Adaptive Voltage Scaling [AVS])

  – Dynamic Voltage Frequency Scaling (DVFS)

  • Real-Time Clock (RTC)

  – Real-Time Date (Day-Month-Year-Day of Week)and Time (Hours-Minutes-Seconds) Information

  – Internal 32.768-kHz Oscillator, RTC Logic and1.1-V Internal LDO

  – Independent Power-on-Reset(RTC_PWRONRSTn) Input

  – Dedicated Input Pin (EXT_WAKEUP) forExternal Wake Events

  – Programmable Alarm Can be Used to GenerateInternal Interrupts to the PRCM (for Wakeup) orCortex-A8 (for Event Notification)

  – Programmable Alarm Can be Used WithExternal Output (PMIC_POWER_EN) to Enablethe Power Management IC to Restore Non-RTCPower Domains

  • Peripherals

  – Up to Two USB 2.0 High-Speed OTG PortsWith Integrated PHY

  – Up to Two Controller-Area Network (CAN) Ports

  – Supports CAN Version 2 Parts A and B

  – Up to Two Multichannel Audio Serial Ports(McASPs)

  – Transmit and Receive Clocks up to 50 MHz

  – Up to Four Serial Data Pins per McASP PortWith Independent TX and RX Clocks

  – Supports Time Division Multiplexing (TDM),Inter-IC Sound (I2S), and Similar Formats

  – Supports Digital Audio Interface Transmission(SPDIF, IEC60958-1, and AES-3 Formats)

  – FIFO Buffers for Transmit and Receive (256Bytes)

  – Up to Six UARTs

  – All UARTs Support IrDA and CIR Modes

  – All UARTs Support RTS and CTS FlowControl

  – UART1 Supports Full Modem Control

  – Up to Two Master and Slave McSPI SerialInterfaces

  – Up to Two Chip Selects

  – Up to 48 MHz

  – Up to Three MMC, SD, SDIO Ports

  – 1-, 4- and 8-Bit MMC, SD, SDIO Modes

  – MMCSD0 has Dedicated Power Rail for 1.8‑Vor 3.3-V Operation

  – Up to 48-MHz Data Transfer Rate

  – Supports Card Detect and Write Protect

  – Complies With MMC4.3, SD, SDIO 2.0Specifications

  – Up to Three I2C Master and Slave Interfaces

  – Standard Mode (up to 100 kHz)

  – Fast Mode (up to 400 kHz)

  – Up to Four Banks of General-Purpose I/O(GPIO) Pins

  – 32 GPIO Pins per Bank (Multiplexed WithOther Functional Pins)

  – GPIO Pins Can be Used as Interrupt Inputs(up to Two Interrupt Inputs per Bank)

  – Up to Three External DMA Event Inputs that canAlso be Used as Interrupt Inputs

  – Eight 32-Bit General-Purpose Timers

  – DMTIMER1 is a 1-ms Timer Used forOperating System (OS) Ticks

  – DMTIMER4–DMTIMER7 are Pinned Out

  – One Watchdog Timer

  – 12-Bit Successive Approximation Register(SAR) ADC

  – 200K Samples per Second

  – Input can be Selected from any of the EightAnalog Inputs Multiplexed Through an 8:1

  Analog Switch

  – Up to Three Enhanced High-Resolution PWMModules (eHRPWMs)

  – Dedicated 16-Bit Time-Base Counter WithTime and Frequency Controls

  – Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge

  Asymmetric Outputs

  • Device Identification

  – Contains Electrical Fuse Farm (FuseFarm) ofWhich Some Bits are Factory Programmable

  – Production ID

  – Device Part Number (Unique JTAG ID)

  – Device Revision (Readable by Host ARM)

  • Debug Interface Support

  – JTAG and cJTAG for ARM (Cortex-A8 andPRCM), PRU-ICSS Debug

  – Supports Device Boundary Scan

  – Supports IEEE 1500

  • DMA

  – On-Chip Enhanced DMA Controller (EDMA) hasThree Third-Party Transfer Controllers (TPTCs)and One Third-Party Channel Controller(TPCC), Which Supports up to 64

  Programmable Logical Channels and EightQDMA Channels. EDMA is Used for:

  – Transfers to and from On-Chip Memories

  – Transfers to and from External Storage(EMIF, GPMC, Slave Peripherals)

  • Inter-Processor Communication (IPC)

  – Integrates Hardware-Based Mailbox for IPC andSpinlock for Process Synchronization BetweenCortex-A8, PRCM, and PRU-ICSS

  – Mailbox Registers that Generate Interrupts

  – Four Initiators (Cortex-A8, PRCM, PRU0,PRU1)

  – Spinlock has 128 Software-Assigned LockRegisters

  • Security

  – Secure Boot

  • Boot Modes

  – Boot Mode is Selected Through BootConfiguration Pins Latched on the Rising Edge

  of the PWRONRSTn Reset Input Pin

  • Package:

  – 324-Pin S-PBGA-N324 Package(ZCZ Suffix), 0.80-mm Ball Pitch

  AMIC110应用:

  • Industrial Communications

  • Connected Industrial Drives

  • Backplane I/O

aaaa

  图1.AMIC110功能框图

  AMIC110工业通信引擎AMIC110 ICE

  The AMIC110 Industrial Communications Engine (ICE) is a development platform targeted at industrial communications and industrial ethernet in particular. Key to the AMIC110 ICE is the Sitara AMIC110 SoC that features ARM® Cortex™-A8 Processor along with the Programmable-Realtime Unit Industrial Communications Sub-System (PRU-ICSS) that enables the integration of real-time industrial protocols, without needing ASIC or FPGA. With a boosterpack form factor, the AMIC110 ICE can be used in conjunction with C2000 Launch pads for developing solutions for Connected Motor Drives, as well as Industrial Sensors and IOs in Factory Automation.

  工业通信引擎AMIC110 ICE主要特性:

  • AMIC110 is based on the Sitara ARM Cortex-A8 32-bit RISC processor at 300 MHz

  • 512MB of DDR3

  • 8MB of SPI Flash

  • 32KB of I2C EEPROM

  • Two 10/100 industrial Ethernet connectors with external magnetics

  • RoHS compliant design

  • 20-pin JTAG header to support all types of external emulators

  • EMC compliant, industrial temperature dual-port EtherCAT slave with an SPI interface

  • 5-V input supply, single-chip power management IC (TPS650250) to power the entire board

  • AMIC110 can be configured to boot EtherCAT firmware from SPI Flash and also supports boot throughthe SPI host processor

  • No DDR or other external RAM required when the EtherCAT slave stack runs on an external hostprocessor (such as the C2000™)

  • Texas Instruments™ LaunchPad™ compatible BoosterPack™ format

  • 3.3-V SPI interface to C2000 F28069M LaunchPad

  工业通信引擎AMIC110 ICE特性应用:

  • Industrial drivers

  • Industrial sensors

  • Factory automation and control

工业通信引擎AMIC110 ICE外形图(正面)

  图2.工业通信引擎AMIC110 ICE外形图(正面)

工业通信引擎AMIC110 ICE外形图(背面)

  图3.工业通信引擎AMIC110 ICE外形图(背面)

工业通信引擎AMIC110 ICE功能框图

  图4.工业通信引擎AMIC110 ICE功能框图

工业通信引擎AMIC110 ICE电路图(1)

  图5.工业通信引擎AMIC110 ICE电路图(1)

工业通信引擎AMIC110 ICE电路图(2)

  图6.工业通信引擎AMIC110 ICE电路图(2)

工业通信引擎AMIC110 ICE电路图(3)

  图7.工业通信引擎AMIC110 ICE电路图(3)

工业通信引擎AMIC110 ICE电路图(4)

  图8.工业通信引擎AMIC110 ICE电路图(4)

工业通信引擎AMIC110 ICE电路图(5)

  图9.工业通信引擎AMIC110 ICE电路图(5)

工业通信引擎AMIC110 ICE电路图(6)

  图10.工业通信引擎AMIC110 ICE电路图(6)

工业通信引擎AMIC110 ICE电路图(7)

  图11.工业通信引擎AMIC110 ICE电路图(7)

工业通信引擎AMIC110 ICE电路图(8)

  图12.工业通信引擎AMIC110 ICE电路图(8)

工业通信引擎AMIC110 ICE电路图(9)

  图13.工业通信引擎AMIC110 ICE电路图(9)

  工业通信引擎AMIC110 ICE材料清单:

工业通信引擎AMIC110 ICE材料清单
工业通信引擎AMIC110 ICE材料清单
工业通信引擎AMIC110 ICE材料清单
工业通信引擎AMIC110 ICE PCB元件布局图(顶层)

  图14.工业通信引擎AMIC110 ICE PCB元件布局图(顶层)

工业通信引擎AMIC110 ICE PCB元件布局图(底层)

  图15.工业通信引擎AMIC110 ICE PCB元件布局图(底层)

  德州仪器(Texas Instruments),简称TI,是全球领先的半导体公司,为现实世界的信号处理提供创新的数字信号处理(DSP)及模拟器件技术。除半导体业务外,还提供包括传感与控制、教育产品和数字光源处理解决方案。TI总部位于美国德克萨斯州的达拉斯,并在25多个国家设有制造、设计或销售机构。

  德州仪器 (TI) 是全球领先的数字信号处理与模拟技术半导体供应商,亦是推动因特网时代不断发展的半导体引擎。

  ----作为实时技术的领导者,TI正在快速发展,在无线与宽带接入等大型市场及数码相机和数字音频等新兴市场方面,TI凭借性能卓越的半导体解决方案不断推动着因特网时代前进的步伐!

  ----TI预想未来世界的方方面面都渗透着 TI 产品的点点滴滴,您的每个电话、每次上网、拍的每张照片、听的每首歌都来自 TI数字信号处理器(DSP) 及模拟技术的神奇力量。

  2011年4月5日,德州仪器(TI)和美国国家半导体(NS)宣布签署合并协议,TI将以25美元/股、总额约65亿美元的现金价格,收购国家半导体。本次收购将使业界共同致力于解决客户模拟问题的两个领导者实现强强联手。

  德州仪器也是图形计算器的重要生产商,其生产的TI 图形计算器系列享誉全球。

  详情请见:

sprr277.pdf

sprr279.pdf

amic110.pdf

sprr276.pdf

spruie6.pdf




责任编辑:Davia

【免责声明】

1、本文内容、数据、图表等来源于网络引用或其他公开资料,版权归属原作者、原发表出处。若版权所有方对本文的引用持有异议,请联系拍明芯城(marketing(at)iczoom.com),本方将及时处理。

2、本文的引用仅供读者交流学习使用,不涉及商业目的。

3、本文内容仅代表作者观点,拍明芯城不对内容的准确性、可靠性或完整性提供明示或暗示的保证。读者阅读本文后做出的决定或行为,是基于自主意愿和独立判断做出的,请读者明确相关结果。

4、如需转载本方拥有版权的文章,请联系拍明芯城(marketing(at)iczoom.com)注明“转载原因”。未经允许私自转载拍明芯城将保留追究其法律责任的权利。

拍明芯城拥有对此声明的最终解释权。

标签: TI

相关资讯